Design Verification Engineer - Low-Latency FPGA/ASIC

Hudson River Trading; New York (NY); Hybrid; USD 270,000 - 330,000; Full time

Job summary

Hudson River Trading (HRT) seeks a Design Verification engineer to craft testbenches and verification environments for high-performance hardware across FPGA/ASIC platforms. You will work with RTL teams, write Python-based tests, and contribute to open-source tooling like Cocotb.

Join a fast-paced team focused on correctness and robustness in a real-time trading environment, with opportunities to influence verification strategies and tooling choices.

Qualifications

• Superb debugging and analytical skills.
• Experience with RTL functional verification.
• Proficiency in Python.
• Familiarity with Cocotb preferred
• C++ experience is a plus
• A bachelor’s degree in computer engineering, computer science or a related field

Responsibilities

• Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
• Quickly root-cause RTL bugs
• Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
• Managing test suites and continuous integration infrastructure
• Developing and improving open-source and internal tools

Skills

RTL verification

Python

Debugging

C++

Education

Bachelor's degree in computer engineering, computer science or a related field

Tools

Cocotb

C++

Job description

Hudson River Trading (HRT) seeks a Design Verification engineer to craft testbenches and verification environments for high-performance hardware across FPGA/ASIC platforms. You will work with RTL teams, write Python-based tests, and contribute to open-source tooling like Cocotb.

Join a fast-paced team focused on correctness and robustness in a real-time trading environment, with opportunities to influence verification strategies and tooling choices.