FPGA/ASIC Hardware Engineer — Low-Latency Systems

Hudson River Trading

New York (NY)

On-site

USD 270,000 - 330,000

Full time

9 days ago

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Job summary

Hudson River Trading (HRT) is hiring for a hardware-focused role in New York. You will design and verify high-performance compute engines using FPGA/ASIC, implementing on-the-fly market data transformations and RTL models on a collaborative global team.

Prior internship in digital logic design is a plus. The team emphasizes rigorous design, verification, and learning, with a base salary around the stated figure and performance bonuses.

Qualifications

  • Pursuing BS/MS/PhD in CS/CE/EE with eligibility for full-time in 2027.
  • Proficiency in SystemVerilog.
  • Deep knowledge of FPGA internals and/or ASIC.
  • Excellent digital logic design, optimization, debugging and problem solving.
  • Thorough understanding of computer architecture and vendor tool suites.
  • Familiarity with C++ and/or Python.
  • Comfortable working in a Linux environment.
  • Previous internship experience in digital logic design.
  • Expertise in networking protocols, CPU design, physical design, or ML accelerators is a big plus.

Responsibilities

  • Contribute to a highly collaborative team, delivering hardware solutions.
  • Describe and communicate hardware designs at various abstraction levels.
  • Analyze and fix problems quickly.
  • Continuously learn, tinker, and explore new technologies to deepen hardware expertise.
  • Challenge teammates and raise the bar for the team's output.

Skills

SystemVerilog
FPGA internals
C++
Python
Linux
Digital logic design
Problem solving

Education

Bachelor's/Master's/PhD in CS/CE/EE

Tools

Linux

Job description

Hudson River Trading (HRT) is hiring for a hardware-focused role in New York. You will design and verify high-performance compute engines using FPGA/ASIC, implementing on-the-fly market data transformations and RTL models on a collaborative global team.

Prior internship in digital logic design is a plus. The team emphasizes rigorous design, verification, and learning, with a base salary around the stated figure and performance bonuses.

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