Design Verification Engineer — Open-Source FPGA/ASIC

Hudson River Trading; New York (NY); On-site; USD 270,000 - 330,000; Full time

Benefits offered by this job

Discretionary bonuses

Competitive benefits package

Open-source project involvement

Job summary

Hudson River Trading is seeking a Design Verification engineer to join our Hardware team in New York. You will write testbenches, verification plans and robust environments for FPGA/ASIC based compute engines used in ultra-low latency trading.

Candidates excel in RTL verification, Python and Linux, with Cocotb familiarity; C++ a plus. You will collaborate with designers, maintain test suites and contribute to open-source toolchains that power our platforms.

Qualifications

• Expertise in RTL verification and testbench development.
• Strong Python scripting and Linux familiarity.
• C++ experience is a plus and Cocotb preferred.

Responsibilities

• Create testbenches and tests for hardware platform.
• Write detailed verification plans and maintain CI/integration workflows.
• Root-cause RTL bugs and collaborate with designers for bringup.

Skills

RTL verification

Python

Linux

C++ experience

Cocotb

Testbench development

Education

Bachelor's degree in CS/CE

Tools

Cocotb

Verilator

Slang

Job description

Hudson River Trading is seeking a Design Verification engineer to join our Hardware team in New York. You will write testbenches, verification plans and robust environments for FPGA/ASIC based compute engines used in ultra-low latency trading.

Candidates excel in RTL verification, Python and Linux, with Cocotb familiarity; C++ a plus. You will collaborate with designers, maintain test suites and contribute to open-source toolchains that power our platforms.