High-Speed FPGA/ASIC Verification Engineer

Hudson River Trading; New York (NY); On-site; USD 200,000 - 300,000; Full time

Job summary

Hudson River Trading (HRT) is seeking experienced Design Verification engineers to build robust testbenches for FPGA/ASIC platforms. You will collaborate directly with designers to rapidly bring up new projects and debug complex RTL issues in a fast-paced, real-time environment.

The ideal candidate has 2+ years of RTL verification experience, strong SystemVerilog/UVM skills, Python proficiency, and familiarity with Verilator or Cocotb; C++ is a plus. No financial trading experience required.

Qualifications

• 2+ years of RTL functional verification experience for FPGA or ASIC
• Experience with code and functional coverage collection/analysis
• Proficiency in SystemVerilog and UVM
• Strong Python skills
• Familiarity with Verilator and Cocotb preferred
• C++ experience a plus

Responsibilities

• Create testbenches and tests for hardware platform using a hybrid open-source/proprietary environment
• Root-cause RTL bugs quickly
• Collaborate with designers for rapid bringup of new projects
• Manage test suites and CI infrastructure
• Develop and improve open-source and internal tools

Skills

RTL verification

SystemVerilog

UVM

Python

Verilator

Cocotb

C++

Education

Bachelor's degree

CS/EE degree

Job description

Hudson River Trading (HRT) is seeking experienced Design Verification engineers to build robust testbenches for FPGA/ASIC platforms. You will collaborate directly with designers to rapidly bring up new projects and debug complex RTL issues in a fast-paced, real-time environment.

The ideal candidate has 2+ years of RTL verification experience, strong SystemVerilog/UVM skills, Python proficiency, and familiarity with Verilator or Cocotb; C++ is a plus. No financial trading experience required.