Apple Entry Level Jobs

Apple; Honolulu (HI); On-site; USD 27,552 - 41,328; Full time

Job summary

Apple in Honolulu, Hawaii is seeking a SoC Physical Design Engineer to drive physical design from netlist to tapeout. You will collaborate with FE/PD teams to optimize floorplanning, clock and power distribution, and ensure timing closure and physical checks meet tight schedules. Bachelor degree required; on-site role with competitive hourly pay.

The position emphasizes teamwork, milestone adherence, and delivering high-performance SOCs for next-generation Apple devices.

Qualifications

• BS with 2+ years of industry experience in chip/SoC design.
• Proficiency in floorplanning, clock/power distribution, timing closure.
• Familiarity with high-level P&R concepts and physical verification.

Responsibilities

• Collaborate with FE to understand chip engineering and drive physical angles early in the design cycle.
• Coordinate with physical design teams to drive processes, set rules, track progress and meet schedules.
• Be a focal point for placement and routing, plan objectives and milestones, understand top/STA/blocking relationships.
• Resolve design and flow issues, identify solutions, and drive execution.

Skills

Floorplanning

Clock distribution

Power distribution

Timing closure

Physical verification

Electrical checks

High-Level Synthesis

SOC design experience

Team collaboration

Education

Bachelor degree

Tools

EDA tools

Job description

Job Title: SoC Physical Design Engineer

Company: Apple

Location: Honolulu, USA

Salary: $20-30 per hour

Educational Requirements: Bachelor Degree

At Apple, novel thoughts have an approach to becoming exceptional items, administrations, and client encounters rapidly. Carry energy and devotion to your work and who knows what you could achieve. Dynamic, dedicated individuals and moving, creative advancements are the standard here. Individuals who work here have rethought whole ventures with all Apple Equipment items. The very enthusiasm for advancement that goes into our items likewise applies to our works on reinforcing our obligation to leave the world better than we tracked down it. Go along with us to assist with conveying the following notable Apple item! In this exceptionally apparent job, you will be liable for executing total chip plan from netlist to tapeout.

Key Capabilities

• Least BS and 2+ long stretches of applicable industry experience.
• Educated in parcel or high level P&R execution, including floorplanning, clock and power circulation, timing conclusion, physical and electrical check.
• Experience with High Level an or more, yet not needed.
• Solid information on actual plan development and investigation streams and system.
• Shown capacity to stick to severe timetable and pass on size prerequisites.
• Solid relational abilities.
• Experienced with industry standard instruments, grasping their capacities and fundamental calculations.
• Experience with enormous SOC plans (>20M doors) with frequencies in over abundance of 1GHz.

Portrayal

• Work with the FE group to comprehend chip engineering and drive actual angles right off the bat in the plan cycle.
• Work with the actual plan group to drive procedures and “most popular strategies” to smooth out actual plan work, concoct rules and agendas, drive execution, and track progress.
• Be a point of convergence for spot and course, drive the work among spot and course designs, put forth objectives and achievements, plan short and long haul work, comprehend conditions between various spaces like top, STA, block spot and course.
• Resolve plan and stream issues connected with actual plan, distinguish likely arrangements, and drive execution.