Engineering Intern: Neural Network Hardware Design

Rivian; Palo Alto (CA); On-site; USD 6,199,000 - 7,026,000; Full time

Benefits offered by this job

Paid vacation

Paid sick leave

Medical insurance benefits

Job summary

Rivian in Palo Alto is seeking an Engineering Intern to work on our Neural Network Engine (NNE) Hardware design. This role is part of our Spring Co-op program and requires you to be onsite for the full duration (Jan–Aug 2027) while enrolled in an accredited program.

You will synthesize RTL for NNE blocks, run simulations, analyze performance, and collaborate with cross‑functional teams to advance our silicon and autonomy goals. Visa sponsorship is not available.

Qualifications

• Must be currently pursuing a bachelor’s, master’s, or PhD in an accredited program.
• Actively pursuing a degree in Electrical or Computer Engineering.

Responsibilities

• Design synthesizable RTL for NNE blocks and interfaces.
• Integrate with other modules and verify functionality.
• Model and analyze performance, power, and timing.

Skills

SystemVerilog RTL design

Python

CPU/GPUs logic design

ML HW/SW exposure

Education

Bachelor's/Master's/PhD in Electrical or Computer Engineering

Tools

eCAD programs

Job description

Rivian in Palo Alto is seeking an Engineering Intern to work on our Neural Network Engine (NNE) Hardware design. This role is part of our Spring Co-op program and requires you to be onsite for the full duration (Jan–Aug 2027) while enrolled in an accredited program.

You will synthesize RTL for NNE blocks, run simulations, analyze performance, and collaborate with cross‑functional teams to advance our silicon and autonomy goals. Visa sponsorship is not available.