Neural Engine Verification Intern — AI Hardware

Rivian Automotive; Palo Alto (CA); On-site; USD 62,000 - 70,000; Full time

Job summary

Rivian Internship Program seeks student candidates to work onsite in Palo Alto, full-time over the Spring Co-op period Jan–Aug 2027. You will evaluate neural engine silicon development, build performance models, and develop ASIC tools with a focus on safety and ISO 26262 alignment.

Eligibility requires enrollment as an undergraduate or graduate student with planned graduation between December 2027 and 2029. Visa sponsorship is not available for this role.

Qualifications

• Must be currently pursuing a bachelors, masters, or PhD degree at an accredited university
• Actively pursuing a degree or one closely related in Electrical or Computer Engineering
• Fundamentals of Computer architecture
• CPU and Memory hierarchy
• C/Python coding skills
• System verilog language

Responsibilities

• Experiment with AI tools for Silicon development: Leverage LLMs and generative agents to automate RTL generation, code documentation, and bug localization within the DLA (Deep Learning Accelerator) pipeline.
• Understand system architecture and develop tools for performance modeling and testing: Build bit-accurate C++/SystemC models to validate the throughput of neural network layers against "golden" ML frameworks like PyTorch.
• Develop tools and verification collateral for large-scale ASIC development: Create scalable UVM-based testbench components and automated regression scripts to support high‑complexity SoC integration.
• Interconnect & Latency Analysis: Architect and implement performance monitors for Interconnect/AXI interfaces to analyze how on chip network impacts real‑time inference latency.
• Safety‑Aware Verification & Fault Injection: Design automated verification collateral to simulate hardware‑level faults, ensuring that safety mechanisms correctly detect errors according to ISO 26262 automotive standards.

Skills

C/Python coding

SystemVerilog

Computer architecture

CPU & memory hierarchy

Job description

Rivian Internship Program seeks student candidates to work onsite in Palo Alto, full-time over the Spring Co-op period Jan–Aug 2027. You will evaluate neural engine silicon development, build performance models, and develop ASIC tools with a focus on safety and ISO 26262 alignment.

Eligibility requires enrollment as an undergraduate or graduate student with planned graduation between December 2027 and 2029. Visa sponsorship is not available for this role.