Design Verification Intern — Edge AI Processor (On-Site Bay Area)

quadric; Burlingame (CA); On-site; USD 69,000 - 79,000; Part time

Benefits offered by this job

Catered lunch

Downtown Burlingame office

Mentorship and project ownership

Job summary

Quadric, based in Burlingame, CA, offers an internship to support the Design Verification team as they validate a next‑generation GPNPU. You will help document test plans, write and debug tests, and generate coverage, gaining insight into CPU/GPU verification methodologies and working directly with architects and designers.

The role emphasizes collaboration, problem solving, and clear technical communication, with hands‑on fluency in SystemVerilog, SystemC, or C/C++, and exposure to Python.

Qualifications

• Currently pursuing Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related field.
• Familiarity with verification methodologies for CPU or GPU designs.
• Proficient in SystemVerilog, SystemC, or C/C++ (UVM is a plus).
• Prepared to document test plans, write and debug tests, and generate coverage.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Responsibilities

• Document test plans for the GPNPU.
• Write and debug tests against the processor's architecture and micro-architecture.
• Generate and analyze coverage to help assess verification completeness.
• Work closely with hardware architects and designers to understand design intent and clarify verification requirements.

Skills

SystemVerilog

SystemC

C/C++

Python

Verification methodologies

Debugging

Technical communication

Problem solving

Education

Bachelor's, Master's, or PhD in CS/EE

Tools

UVM

Job description

Quadric, based in Burlingame, CA, offers an internship to support the Design Verification team as they validate a next‑generation GPNPU. You will help document test plans, write and debug tests, and generate coverage, gaining insight into CPU/GPU verification methodologies and working directly with architects and designers.

The role emphasizes collaboration, problem solving, and clear technical communication, with hands‑on fluency in SystemVerilog, SystemC, or C/C++, and exposure to Python.