RTL SoC Design Intern

quadric, Inc; Burlingame (CA); On-site; USD 69,000 - 79,000; Full time

Benefits offered by this job

Catered lunch

Downtown Burlingame

Disruptive culture

Job summary

Quadric is building edge AI with a GPNPU; we’re seeking a motivated intern to join the Burlingame team, contributing to SoC subsystem development and integrating third‑party IP. You’ll help optimize PPA and work with architects on front-end design, gaining hands-on experience in a real FPGA/ASIC environment.

You will collaborate with engineers on subsystem integration, verify design intent, and document technical decisions while developing proficiency in SystemVerilog/Verilog and Python

Qualifications

• Pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Responsibilities

• Support SoC Subsystem Development and integration of subsystems and third-party IP.
• Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
• Collaborate closely with SoC architects/designers and communicate findings clearly.

Skills

SystemVerilog

SoC frontend design

Problem-solving

Technical communication

Python scripting

Education

Bachelor's / Master’s / PhD in Electrical Engineering or Computer Engineering

Job description

Quadric is redefining edge AI with the industry’s first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world’s first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow’s technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

The Opportunity

This is a chance to get hands-on experience building a next-generation SoC architecture from the ground floor, working directly alongside our hardware team as we bring supercomputer technology to the Edge.

You’ll support the SoC design team with subsystem development, third-party IP integration, and PPA (power, performance, area) optimization for Quadric’s GPNPU platform — gaining exposure to real front-end design and integration methodologies, and working closely with the architects who define the chip.

Note: Our preference is for this internship to be based out of our Burlingame, California office. Candidates should be based in the Bay Area or able to relocate for the internship period and available to work on site.

What You’ll Do

Support SoC Subsystem Development

• Help design and integrate SoC-level subsystems, working alongside engineers integrating third-party IP (such as NoC, PCIe/UCIe interfaces, DDR, Security, etc.).
• Contribute to documentation of SoC architecture and application requirements.

Support PPA Optimization

• Assist in analyzing and optimizing Power, Performance, and Area (PPA) at the SoC level.
• Get exposure to low-power digital design techniques and timing closure work across front-end stages.

Collaborate Across the Team

• Work closely with SoC architects and designers to understand design intent and integration requirements.
• Communicate findings, blockers, and technical questions clearly to the team.

What Success Looks Like

Within your internship, you’ll:

• Build a working understanding of SoC subsystem development and integration.
• Contribute analysis or documentation that meaningfully supports PPA optimization efforts.
• Develop hands-on fluency with SystemVerilog or Verilog in a real front-end design environment.

What We’re Looking For

Required

• Currently pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Familiarity with SoC/ASIC front-end design concepts.
• Proficient in SystemVerilog or Verilog.
• Prepared to collaborate with architects and designers on subsystem development and integration tasks.
• Demonstrated capability in problem-solving, debugging, and clear technical communication.

Preferred

• Coursework or project experience with computer architecture, low-power design, or RTL design.
• Exposure to logic synthesis, FPGA design, or performance modeling.
• Adept with scripting languages like Python and using LLMs to get things done

What We Offer

The hourly salary range for this temporary position is $50-57/hr . This range reflects the full span of levels and geographies at which Quadric hires for this role. The actual hourly salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies.

Quadric interns receive hands-on experience working alongside industry experts in AI and semiconductor technology, with access to mentorship and meaningful project ownership from day one along with following

• Catered lunch each day in our office
• Downtown Burlingame office location, close to shops, cafes, and local amenities
• A work culture focused on innovative disruption

Equal Employment Opportunity

Quadric is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, sexual orientation, gender identity, marital status, medical condition, or any other characteristic protected by applicable federal, state, or local law

E-Verify and Right to Work Notices

Quadric participates in the E-Verify program to confirm employment eligibility for U.S.-based roles. As part of this process, applicants may review the following notices, which explain your rights and our participation in E-Verify. These notices are provided in English and Spanish.

• E-Verify Participation Notice (English | Spanish)
• Right to Work Notice (English | Spanish)

No action is required from candidates during the application process. These notices are provided for informational purposes only.

Privacy

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