DSP & System Validation Engineer: High-Speed Optical ASIC

OpenTalent

Wayne (CA)

On-site

USD 180,000 - 240,000

Full time

14 days+
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Benefits offered by this job

Annual bonus
Equity awards
Equity grant

Job summary

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products. You will validate the ASIC architecture pre- and post-silicon, ensuring performance, power, and cost targets are met throughout the project lifecycle.

The role requires deep DSP knowledge, Verilog coding, and experience with MATLAB/Simulink. Familiarity with front-end tools (NCVerilog, NCSIM, SimVision, SpyGlass) and DFT-friendly RTL

Qualifications

  • MS with 10+ years or PhD with 7+ years in DSP design for SerDes and data center networking.
  • Post-silicon validation experience for mixed-signal IPs.
  • Knowledge of 100G/200G/400G PAM4/NRZ trade-offs for performance, power, cost.

Responsibilities

  • Design digital signal processing blocks for SerDes and high-speed data center connectivity.
  • Validate ASIC architecture pre- and post-silicon.
  • Translate CDR and equalization architectures into Verilog for synthesis.
  • Work with Matlab/Simulink and front-end tools; support DFT-friendly RTL.

Skills

Digital signal processing
System validation
Verilog/SystemVerilog
Matlab/Simulink
High-speed SerDes
DFT/RTL debugging

Education

MS in Electrical Engineering or Computer Engineering
PhD in Electrical Engineering or Computer Engineering

Tools

Verilog-HDL/SystemVerilog
NCVerilog
NCSIM
SimVision
SpyGlass

Job description

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products. You will validate the ASIC architecture pre- and post-silicon, ensuring performance, power, and cost targets are met throughout the project lifecycle.

The role requires deep DSP knowledge, Verilog coding, and experience with MATLAB/Simulink. Familiarity with front-end tools (NCVerilog, NCSIM, SimVision, SpyGlass) and DFT-friendly RTL

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