Digital Signal Processing and System Validation Engineer

Broadcom

San Jose (CA)

On-site

USD 250,000 - 350,000

Full time

14 days+
Application generator

A complete application in a minute — tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-generation optical data center connectivity products and validate ASIC architecture pre- and post-silicon.

You will work on high-speed SerDes design, PAM4/NRZ architectures, and DFT-friendly RTL, collaborating with teams across hardware and software to optimize performance, power and cost for scalable data center interconnects.

Qualifications

  • MS in Electrical or Computer Engineering with 10+ years or PhD with 7+ years in DSP for SerDes and data-center networking.
  • Post-silicon validation of digital and analog mixed-signal IPs.
  • Deep understanding of 100G/200G/400G PAM4 and NRZ per-lane trade-offs.
  • Translate CDR and equalization architectures into Verilog for synthesis.
  • Proficiency in Matlab, Simulink and Verilog/SystemVerilog.
  • Front-end tools: NCVerilog, NCSIM, Simvision, Spyglass.
  • DFT-friendly RTL and understanding of scan concepts.
  • Synthesis, CDC, static timing analysis.
  • SDF annotated simulations and awareness of parasitic delays.

Skills

DSP design expertise
Verilog/SystemVerilog
Matlab/Simulink
Front-end ASIC tools
DFT RTL design
Synthesis/STA/CDC
Parasitic delay modeling

Education

MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years in DSP for SerDes and data-center networking

Tools

NCVerilog
NCSIM
Simvision
Spyglass

Job description

Please Note:

Job Description:

Broadcom is looking for a Digital Signal Processing and System Validation Engineer. In this highly visible role, you will be designing digital signal processing blocks for the next generation of optical data center connectivity products. You will be responsible for validating the ASIC architecture post and pre-silicon.

Qualifications include:

  • MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years of experience in digital signal processing design for SerDes and serial link high-speed data center networking.
  • Experience in post silicon validation of digital and analog mixed-signal IPs.
  • Deep understanding of ADC and analog based optical and electrical interconnect architectures such as 100G/200G/400G per lane PAM4 and NRZ design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.
  • Experience translating CDR and equalization architectures into Verilog code for logic synthesis.
  • Proficient with Matlab, Simulink and Verilog-HDL/System Verilog coding.
  • Experience with front end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
  • Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
  • Experience in synthesis, CDC, static timing analysis.
  • Exposure to SDF annotated simulations with good understanding of parasitic delays.

Highly Desired Qualifications:

  • Good understanding of high speed DSP applications and algorithms.
  • Prior experience of high speed ADC, FFE, DFE, CDR Adaptation algorithms for PAM4 signals.
  • Understanding of logic optimization for low power, timing margins & DFT.
  • Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
  • Understanding & exposure to Verilog AMS simulation, experience in behavioral models of analog circuits will be helpful.
  • Willing to work in a multifunctional role.
  • Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
  • Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
  • Excellent time and task management, and interpersonal skills.

Compensation and Benefits

The annual base salary range for this position is To

As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Digital Signal Processing and System Validation Engineer
Digital Signal Processing and System Validation Engineer

Broadcom Inc. • San Jose (CA), Northern (KY)

Hybrid
USD 180,000 - 260,000
Digital Signal Processing and System Validation Engineer
Digital Signal Processing and System Validation Engineer

Broadcom Inc. • Wayne (CA)

On-site
USD 170,000 - 250,000
Medical, dental and vision plans
401(k) with company matching
Employee stock purchase program
Silicon Design and Validation Engineer
Silicon Design and Validation Engineer

Broadcom Inc. • Wayne (CA)

On-site
USD 120,000 - 192,000
Medical, dental, and vision plans
401(k) with company matching
Paid holidays and sick leave
+1
Senior Serdes System Design Engineer/Architect
Senior Serdes System Design Engineer/Architect

Broadcom • Irvine (CA)

On-site
USD 144,000 - 230,000
Equity grant
Annual equity awards
401K with company match
+1
System Signal/Power Integrity Engineer
System Signal/Power Integrity Engineer

Broadcom • Fort Collins (CO)

On-site
USD 120,000 - 170,000
Medical benefits
401(k) with company match
Equity grants
Senior Serdes System Design Engineer/Architect
Senior Serdes System Design Engineer/Architect

Broadcom Inc. • Austin (TX)

On-site
USD 144,000 - 230,000
Discretionary bonus
Equity grants
401(k) matching
+1
Design Verification Engineer
Design Verification Engineer

Broadcom • Irvine (CA)

On-site
USD 144,000 - 230,000
Annual bonus
Equity grants
Comprehensive benefits package
Physical IC Design Engineer
Physical IC Design Engineer

Socket.dev • San Jose (CA)

On-site
USD 120,000 - 192,000
Medical, dental and vision plans
401(K) participation with matching
Employee Stock Purchase Program (ESPP)
+1
R&D IC Design Engineer
R&D IC Design Engineer

Broadcom Inc. • Irvine (CA)

On-site
USD 160,000 - 210,000
Medical/dental/vision
401(k) with company match
ESPP
+3
R&D IC Design Engineer
R&D IC Design Engineer

Broadcom Inc. • San Jose (CA)

Hybrid
USD 180,000 - 240,000
Medical, dental and vision plans
401(K) with company matching
ESPP
+3