Senior ASIC Design Engineer: DSP/SerDes for Optics

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking an experienced ASIC Design Engineer to develop high-speed digital blocks for optical transceivers and SerDes. You will own complex ASIC blocks and collaborate with DSP, Analog, Verification, and Physical Design teams.

The ideal candidate has 5+ years in digital ASIC design, strong Verilog/SystemVerilog, familiarity with EDA flows, timing, CDC, and RTL simulation. Window for silicon bring-up, tapeout, and optimization across performance, power, and area.

Qualifications

• Bachelor's or higher in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in digital ASIC design with ownership of complex blocks.
• Strong proficiency in Verilog and/or SystemVerilog.
• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Familiarity with DSP, SerDes, analog/mixed-signal ICs, digital communications, optical communications.
• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
• Knowledge of verification methodologies such as UVM and/or formal verification.
• Understanding of low-power design techniques and PPA optimization.
• Excellent communication and teamwork in startup environments.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop mixed-signal ASICs.
• Develop high-speed data paths, signal processing blocks, control logic, and interfaces for optical systems.
• Perform synthesis, timing analysis, lint, formal equivalence, CDC, and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Perform RTL simulation and debugging to ensure design functionality and performance.
• Contribute to block-level and top-level integration, verification, and silicon bring-up.
• Participate in architecture and design reviews and guide other engineers.
• Collaborate with cross-functional teams to troubleshoot design and system issues.
• Develop scripts and automation using Python, Tcl, or similar languages.

Skills

Verilog SystemVerilog

ASIC design

DSP/SerDes knowledge

RTL design

Digital communications

Education

Bachelor's or higher in Electrical/Computer Engineering

Tools

EDA tools

Job description

Celero Communications, Inc. is seeking an experienced ASIC Design Engineer to develop high-speed digital blocks for optical transceivers and SerDes. You will own complex ASIC blocks and collaborate with DSP, Analog, Verification, and Physical Design teams.

The ideal candidate has 5+ years in digital ASIC design, strong Verilog/SystemVerilog, familiarity with EDA flows, timing, CDC, and RTL simulation. Window for silicon bring-up, tapeout, and optimization across performance, power, and area.