High-Speed DSP & Validation Engineer for Data Center ASIC

Broadcom Inc.; Wayne (CA); On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) with company matching

Employee stock purchase program

Job summary

Broadcom Inc. is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next‑gen optical data center connectivity products.

You will validate ASIC architecture pre- and post‑silicon, translating CDR and equalization into Verilog for synthesis and using MATLAB/Simulink for modeling. The role requires deep expertise in high‑speed PAM4/NRZ signaling, front‑end tools, and DFT‑friendly RTL.

Qualifications

• MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years in DSP design for SerDes and data center networking.
• Experience in post-silicon validation of digital and analog mixed-signal IPs.
• Understanding of 100G/200G/400G PAM4 and NRZ per-lane design trade-offs.
• Ability to translate CDR and equalization architectures into Verilog for synthesis.
• Proficiency with MATLAB, Simulink and Verilog‑HDL/SystemVerilog.
• Experience with front end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
• Exposure to Design for Test (DFT) RTL and scan concepts.
• Experience in synthesis, CDC, static timing analysis and SDF annotated simulations.

Responsibilities

• Design digital signal processing blocks for next‑gen optical data center connectivity products.
• Validate ASIC architecture pre‑ and post‑silicon.
• Translate DSP architectures into synthesizable Verilog for logic synthesis.
• Collaborate with cross‑functional teams to optimize performance, power and cost.

Skills

DSP design

SerDes

Data center networking

High-speed signaling

Education

MS in Electrical/Computer Engineering

PhD

Tools

MATLAB

Simulink

Verilog-HDL/SystemVerilog

NCVerilog

NCSIM

Simvision

Spyglass

Job description

Broadcom Inc. is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next‑gen optical data center connectivity products.

You will validate ASIC architecture pre- and post‑silicon, translating CDR and equalization into Verilog for synthesis and using MATLAB/Simulink for modeling. The role requires deep expertise in high‑speed PAM4/NRZ signaling, front‑end tools, and DFT‑friendly RTL.