DSP Hardware Design Engineer — AI/NPU Accelerators

Cadence Design Systems; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Benefits offered by this job

Vacation & holidays

401(k) with match

Employee stock purchase plan

Medical/Dental/Vision coverage

Job summary

Cadence Design Systems in California seeks a senior CPU/DSP/NPU design engineer with an MS in EE/CS and 5+ years of relevant experience. You will contribute to state-of-the-art DSP products, perform logic design for CPUs, DSPs, NPUs and hardware accelerators, and work with Verilog/SystemVerilog and EDA tools.

The role offers a competitive salary, incentive compensation, equity, and a comprehensive benefits package including vacation, 401(k) with match, stock purchase plan, and

Qualifications

• MS in EE/Computer Eng with 5+ years CPU/DSP/NPU/hardware accelerator design experience.
• Strong logic design skills demonstrated by CPU/DSP/NPU/hardware accelerator tape-outs.
• Experience in data-path component design.
• Excellent knowledge of Verilog/SystemVerilog and common EDA tools.
• Experience in AI-native logic design, analysis or optimization workflows.
• Solid understanding of computer architecture and pipelines.
• Experience with scripting languages; Perl is required.
• C/C++ compiler knowledge is a plus.
• Excellent written and verbal communication; self-starter.

Skills

Verilog/SystemVerilog

C/C++

Perl

AI-native logic design

CPU/DSP/NPU design

Data-path design

Pipelined architectures

Scripting languages

Education

MS in EE / Computer Eng

Tools

EDA tools

Job description

Cadence Design Systems in California seeks a senior CPU/DSP/NPU design engineer with an MS in EE/CS and 5+ years of relevant experience. You will contribute to state-of-the-art DSP products, perform logic design for CPUs, DSPs, NPUs and hardware accelerators, and work with Verilog/SystemVerilog and EDA tools.

The role offers a competitive salary, incentive compensation, equity, and a comprehensive benefits package including vacation, 401(k) with match, stock purchase plan, and