NPU RTL Design Engineer — DSP & SoC Architecture

QUALCOMM, Inc.; San Diego (CA); On-site; USD 134,000 - 201,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an NPU RTL Design Engineer in San Diego, CA to advance high-performance Hexagon/NPU cores for multi-tier mobile SOCs.

The role involves RTL development, integration, and collaboration with architecture, verification, and physical design teams to meet timing and power goals. The ideal candidate has a strong background in RTL design, Verilog/SystemVerilog, and microprocessor integration, with experience across linting, CDC, LEC, and CLP tools.

Qualifications

• Bachelor’s degree in EE/CS/CE or related field with 2+ years of relevant work experience; or 1+ year with Master’s; or PhD.
• 2+ years of high-performance microprocessor design experience.

Responsibilities

• Define micro-architecture documentation with system architecture team.
• Develop RTL for Hexagon/NPU blocks for SoC integration.
• Run frontend tools for linting, CDC, and power analysis.
• Collaborate with physical design to meet timing and power constraints.
• Support verification through test plans and coverage.

Skills

RTL design

Verilog

SystemVerilog

Bus interface

Processor integration

Digital design

Cache

Education

Bachelor's degree in Electrical Engineering/Computer Science/Computer Engineering

Master’s degree preferred

PhD in Electrical Engineering/Computer Science/Computer Engineering

Tools

Linting tools

CDC

LEC

CLP

Job description

Qualcomm Technologies, Inc. is seeking an NPU RTL Design Engineer in San Diego, CA to advance high-performance Hexagon/NPU cores for multi-tier mobile SOCs.

The role involves RTL development, integration, and collaboration with architecture, verification, and physical design teams to meet timing and power goals. The ideal candidate has a strong background in RTL design, Verilog/SystemVerilog, and microprocessor integration, with experience across linting, CDC, LEC, and CLP tools.