DPU Power Architect, Infrastructure Silicon

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Job summary

Meta's Infrastructure Silicon organization seeks an experienced Power Architect to drive power modeling, analysis, and architectural power optimization for DPUs and SmartNIC/IPU designs. The role influences architecture from early path-finding to RTL/gate-level power analysis, ensuring best-in-class performance-per-watt on data center workloads.

You will own power budgets, collaborate with design, firmware, and software teams, and correlate pre-silicon projections with post-silicon measurements

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• Experience analyzing workload and power-relevant behaviors.
• Experience building system-level power models and tracking from early estimates through RTL/gate-level power.
• Experience defining or evaluating architectural power-saving features (DVFS, power gating, clock gating).
• Understanding of SoC pipelines and data movement impact on power vs. performance.
• Proficiency in programming languages for model development and automation (Python, C/C++, SystemC).
• Experience driving independent analysis and influencing architectural direction through data.

Responsibilities

• Analyze real-world DPU software use cases to identify hardware power bottlenecks and power-relevant behaviors.
• Build and maintain workload-driven power models and power rollups for DPU architectures, tracking accuracy from early estimates to RTL/gate-level power.
• Quantify architectural trade-offs with respect to PPA and energy-per-transaction to guide design decisions.
• Define and drive structural power-saving features: DVFS, AVS, power gating, clock gating, activity throttling, workload-aware policies.
• Analyze SoC pipelines and data movement paths to optimize power-versus-performance trade-offs.
• Own power budgets and provide power-delivery and thermal inputs with cross-functional teams.
• Correlate pre-silicon projections with post-silicon measurements to improve methodology.

Skills

Workload analysis

Power modeling

System-level modeling

Data-driven decision making

Power optimization

Programming experience

Education

Bachelor's degree in CS/CE or equivalent

PhD (preferred)

Tools

Python

C/C++

SystemC

FSDB/SAIF

Power estimation tools (PrimePower/PTPX, Joules, PowerArtist)

Job description

Summary:

Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are seeking an experienced Power Architect to drive power modeling, analysis, and architectural power optimization of our Data Processing Unit (DPU) designs. In this role you will influence architecture and microarchitecture decisions from early path-finding through RTL/gate-level power analysis and silicon correlation, ensuring our DPUs deliver leading performance-per-watt on real data center workloads.

Required Skills:

DPU Power Architect, Infrastructure Silicon Responsibilities:

1. Analyze and characterize real-world DPU software use cases (network virtualization, storage offload, crypto/compression, packet processing) to identify hardware power bottlenecks and power-relevant behaviors

2. Build and maintain workload-driven, system-level power models and power rollups for current and future SmartNIC/IPU/DPU architectures, tracking accuracy from early analytical estimates through RTL and gate-level power analysis

3. Quantify architectural and micro-architectural trade-offs with respect to PPA, with emphasis on energy-per-transaction, power-per-bit moved, and performance-per-watt, to inform and guide design decisions

4. Define and drive structural power-saving architecture features, including DVFS, AVS, power gating, clock gating, activity throttling, power state management, and workload-aware power policies

5. Analyze SoC pipelines and data movement paths (host-to-DPU, memory/fabric/network traffic) to understand and optimize the power-versus-performance trade-off

6. Own power budgets and provide power-delivery and thermal inputs in partnership with design, physical design, firmware, platform, and software teams

7. Correlate pre-silicon power projections with post-silicon measurements and drive methodology improvements based on findings

Minimum Qualifications:

Minimum Qualifications:

1. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

2. Experience in workload analysis and characterization, and abstracting power-relevant behaviors into models for architectural analysis

3. Experience building system-level power models and power rollups, and tracking them from early estimates through RTL/gate-level power

4. Experience defining or evaluating architectural power-saving features such as DVFS, power gating, and clock gating

5. Understanding of SoC pipelines and how data movement impacts power versus performance

6. Proficiency in programming languages for model development and automation (e.g., Python, C/C++, SystemC)

7. Experience driving analysis independently and influencing architectural direction through data

Preferred Qualifications:

Preferred Qualifications:

1. PhD in Computer Science, Computer Engineering or Electrical Engineering

2. 15+ years of relevant industry experience in power architecture and power modeling for high-performance SoCs

3. Experience with power management firmware/software co-design, on-die power telemetry, and closed-loop power/thermal control

4. Experience with simulation/emulation environments used in ASIC development flows, including emulation-based activity capture (FSDB/SAIF) for long-window power analysis

5. Experience with low-power implementation flows, including multi-voltage/UPF power intent, retention and isolation strategies

6. Experience building or scaling power modeling and power regression infrastructure for hyperscale data center ASICs (network, storage, or AI accelerator designs)

7. Familiarity with post-silicon power measurement, telemetry, and model-to-hardware correlation methodologies

8. Experience with industry-standard power estimation and sign-off tools (e.g., Synopsys PrimePower/PTPX, Cadence Joules, Ansys PowerArtist) for power analysis and optimization

9. Familiarity with power delivery network, voltage droop/di-dt analysis, and rack/platform-level power and thermal constraints

Public Compensation:

$178,000/year to $250,000/year + bonus + equity + benefits

Industry:

Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affipative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].