DPU Networking Architect, Infrastructure Silicon

Meta; Austin (TX); On-site; USD 178,000 - 250,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta’s Infrastructure Silicon organization seeks a DPU Networking Architect to own datapath design for DPUs, NICs, and related offloads. You will decide what runs in hardware, firmware, or host software and define the interfaces between them.

You’ll collaborate with firmware, driver, and RTL teams, backing decisions with performance and PPA analysis. This is a senior role requiring 8+ years in networking datapaths and datacenter experience.

Qualifications

• 8+ years of experience architecting Networking datapaths and packet-processing pipelines for NIC/DPU or ASICs.
• Experience with SmartNIC/IPU/DPU architectures and their usages: virtualization, disaggregation, overlay networking, and offloads.
• Experience with Ethernet, IPv6, TCP/UDP, Geneve, PSP, SRv6 and related offload mechanisms.
• Experience with RDMA and storage protocols such as RoCEv2 and NVMe/NVMe-over-Fabric.
• Experience with on-chip scheduling/ QoS, and datacenter fabric topologies.
• Proven ability to drive architectural direction using data.

Responsibilities

• Architect the Networking datapath for DPUs, including packet processing, virtualization, RDMA, and security.
• Decide what runs in datapath engines, firmware, or host software and design interfaces.
• Define program interfaces and match-action tables for datapath control.
• Collaborate with firmware, driver, and software teams to ensure clean, efficient interfaces.
• Support post-silicon bring-up and resolution of integration issues.

Skills

Networking datapaths

Packet processing

NIC/DPU architectures

RDMA/offloads

PPA/data modeling

Education

PhD in CS/CE/EE

Tools

SystemVerilog

VHDL

SystemC

Python

Job description

Meta’s Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs. We are looking for a Data Processing Unit (DPU) Network Architect to own how our DPUs handle networking: packet processing and offloads, network virtualization and overlays, RDMA and storage transports, and inline security. You’ll decide how the networking datapath is built and where each function belongs – in hardware, in firmware, or in host software – define how software programs it, and carry those decisions from early path-finding through implementation and silicon bring-up. You’ll work hand in hand with the firmware, driver, and RTL teams, backing your calls with performance and PPA analysis where deeper study is needed.

DPU Networking Architect, Infrastructure Silicon Responsibilities:

• Architect the Networking datapath for our DPUs – packet processing and offloads, Network virtualization and overlays, RDMA and storage transports, and inline security – from early path-finding through silicon bring-up
• Decide what runs in the datapath engines, what runs in firmware, and what stays in host software, and design the interfaces between them
• Define how software programs and controls the datapath – match-action tables, rule and flow programming, register and descriptor interfaces, and the offload interfaces firmware and drivers build on
• Work closely with firmware, driver, and software teams so the datapath and its interfaces are clean, efficient, and genuinely usable, and evolve them as needs change
• Work closely with design, DV, and PD teams on feature definition and PPA tradeoff
• refine architecture to meet the design and PD constraints. Define architecture to maximize DV complexity including defining specific features to help ease DV
• Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed
• Support Design, DV and PD to resolve interface and integration issues as they come up. Support post-silicon bring-up of the Networking functionality

Minimum Qualifications:

• 8+ years of relevant industry experience architecting Networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs
• Experience with SmartNIC/IPU/DPU architectures and their usages: Network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and PSP gateways, including offload mechanisms
• Experience with datacenter Networking technologies and protocols such as Ethernet, IPv6, TCP/UDP, Geneve, PSP, and SRv6, including offload mechanisms for TCP segmentation, reassembly, checksum, and receive-side scaling
• Experience with RDMA and storage protocols and fabrics, including RoCEv2 and NVMe/NVMe-over-Fabric (TCP and RDMA)
• Experience with congestion control (e.g., DCQCN) and emerging transports such as UET and comparable next-generation RDMA transports
• Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms — transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) — and their impact on latency, fairness, bandwidth partitioning, and throughput
• Experience with datacenter network topologies and fabric architectures (e.g., Clos/fat-tree, rail‑optimized fabrics) and their performance implications, including oversubscription, ECMP/load balancing, and end‑to‑end latency and congestion behavior
• Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., IPSec, PSP)
• Experience with domain‑specific dataplane languages such as P4
• Experience with data center workloads and their networking characteristics
• Experience with analytical performance‑modeling methods (e.g., queueing theory, Little’s Law, bandwidth-delay/outstanding‑transaction sizing)
• Experience driving analysis independently and influencing architectural direction through data

Preferred Qualifications:

• PhD in Computer Science, Computer Engineering or Electrical Engineering
• 15+ years of relevant industry experience architecting networking datapaths and packet‑processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs
• Experience designing high‑performance offload architectures for NVMe‑over‑Fabric
• Experience designing data‑plane offload/acceleration architectures using programmable processors/engines (programmable parsers, match‑action, etc.)
• Experience designing high‑performance inline data encryption engines, such as for IPSec and PSP
• Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows
• Experience with GPU, machine learning, multi‑threaded programming paradigm
• Experience with emerging RDMA transports such as UET and comparable next‑generation RDMA protocols
• Experience with post‑silicon performance validation and model‑to‑hardware correlation methodologies
• Experience with performance modeling and workload characterization for networking architectures, including analytical methods (e.g., queueing theory, Little’s Law) and frameworks such as SystemC
• Experience with high‑level synthesis, power‑performance‑area trade‑off analysis, or PPA‑driven microarchitectural optimization
• Experience designing scheduling, arbitration, or rate‑limiting/traffic‑management hardware (e.g., hierarchical schedulers, WRR/DWRR/strict‑priority arbiters, shapers/policers)
• Experience developing Python‑based automation pipelines for simulation orchestration, regression testing, and performance data analysis

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

Meta is proud to be an Equal Employment Opportunity and Aff…

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$178,000/year to $250,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.