Digital Verification Engineer – PCIe/RISC-V, UVM expert

Arago; Paris (TX); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Stock options

Relocation support

Healthcare coverage

Pension contributions

25 days PTO

Public transport subsidy

Growth opportunities

Job summary

Arago is seeking a senior verification engineer to ensure the functional integrity, performance, and reliability of next-generation optical chips. You will wield SystemVerilog, UVM, and modern verification environments to verify high-speed interfaces and PCIe components.

You will collaborate with architects, designers, and customers, plan end-to-end ASIC verification, and support bring-up and post-silicon validation.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Proven fluency and hands-on expertise in SystemVerilog for verification.
• Demonstrated prior experience with the UVM framework and modern verification environments.
• Direct knowledge of AXI/AXIStream, APB/AHB, I2C, JTAG, PCIe and experience verifying digital logic for high-speed interfaces.
• Practical experience verifying RISC-V CPU designs or equivalent digital processor architectures within an ASIC context.
• Strong analytical and communication skills for customer-driven projects and interdisciplinary teamwork.
• Language: English at a proficient level. French is a plus.

Responsibilities

• Develop robust verification plans for complex digital and mixed-signal optical chip designs.
• Collaborate with architects, designers, and customers to derive verification strategies and provide actionable feedback.
• Perform netlist-level simulations with SDF back-annotation for timing-accurate verification.
• Support FPGA/ASIC bring-up and post-silicon validation as needed.
• Develop, maintain, and optimize testbenches and verification components using SystemVerilog features (constrained random testing, assertions, TLM) for robust coverage-driven environments.
• Design reusable UVM-based environments and components (agents, monitors, scoreboards) for block- and system-level verification; enable regression automation and coverage closure.
• Develop verification strategies for PCIe endpoints and root complexes; apply protocol checks, compliance suites, error injection, and debugging.
• Contribute to verification of RISC-V cores; craft test plans, use reference models, and perform coverage analysis.
• Plan end-to-end ASIC verification from block-level to full-chip integration; conduct formal verification and issue debugging with cross-functional teams.

Skills

SystemVerilog

UVM

Verilog

PCIe

AXI/AXIStream

I2C/JTAG

RISC-V

Communication

English

Education

Bachelor’s degree in Electrical Engineering/Computer Engineering

Master’s degree in Electrical Engineering/Computer Engineering

PhD in Electrical Engineering/Computer Engineering

Tools

UVM

SDF back-annotation

Verification environments

Job description

Arago is seeking a senior verification engineer to ensure the functional integrity, performance, and reliability of next-generation optical chips. You will wield SystemVerilog, UVM, and modern verification environments to verify high-speed interfaces and PCIe components.

You will collaborate with architects, designers, and customers, plan end-to-end ASIC verification, and support bring-up and post-silicon validation.