Digital Verification Engineer - First Silicon

Apple Inc.; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple Inc. in the San Francisco Bay Area seeks a digital-focused DV engineer to enable first silicon for IP designs. You will drive pre-silicon verification, establish DV methodology, develop test plans and environments, and sign-off for RTL tape-out.

The role emphasizes SystemVerilog/UVM and scalable DV infrastructure for IP/SoC verification. You will create test plans, stress test with SystemVerilog/UVM, debug regressions, and use modern verification tools.

Qualifications

• Experience in SystemVerilog/UVM verification.
• Ability to design test plans and DV environments.
• Experience debugging regressions.
• Familiarity with RTL tape-out sign-off.

Responsibilities

• Drive pre-silicon verification.
• Establish DV methodology and test plans.
• Develop scalable DV infrastructure for IP/SoC verification.
• Sign-off for RTL tape-out.

Skills

SystemVerilog

UVM

DV methodology

pre-silicon verification

Job description

Apple is seeking a digital‑focused DV engineer to enable first silicon for IP designs in the San Francisco Bay Area. You will drive pre‑silicon verification, establish DV methodology, develop test plans and environments, and sign‑off for RTL tape‑out.

The role emphasizes SystemVerilog/UVM and scalable DV infrastructure for IP/SoC verification. Responsibilities include creating test plans, stress testing with SystemVerilog/UVM, debugging regressions, and using modern verification tools.