Digital RTL Design Engineer — STA & Timing Expert

Asteralabs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is seeking a Digital RTL Design Engineer focused on Static Timing Analysis for its San Jose design team. You will translate microarchitectural specs into synthesizable RTL and collaborate with verification, physical design, DFT, firmware, systems, and validation teams to ensure successful tapeout and silicon validation.

You will work on high-performance connectivity ASICs, contribute to timing closure, power optimization, and implementation flows, and help drive robust RTL quality

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field.
• Master’s degree preferred.
• 3+ years of relevant experience in digital ASIC/SoC/RTL design or equivalent.
• Hands-on experience with Verilog or SystemVerilog RTL development.
• Experience with RTL simulation, debugging, synthesis, and basic timing analysis.
• Familiarity with ASIC design flows and cross-functional collaboration.

Responsibilities

• Develop synthesizable Verilog/SystemVerilog RTL for ASIC blocks and subsystems.
• Collaborate with verification teams to define test plans and coverage goals.
• Support STA, timing closure, and power optimization with design and synthesis teams.
• Assist DFT integration, scan, and implementation signoff.
• Document design decisions and participate in silicon bring-up and post-silicon validation.

Skills

Verilog/SystemVerilog RTL

RTL design

Static Timing Analysis (STA)

Synthesis/Implementation flows

UVM verification

Python/Tcl scripting

Cross-functional collaboration

On-site work in San Jose

Education

Bachelor’s degree in Electrical Engineering/Computer Engineering

Master’s degree preferred

Tools

Cadence Genus/Innovus

Synopsys Design Compiler/ICC2

Cadence/PrimaTime

Lint/CDC/RDC tools

Job description

Astera Labs is seeking a Digital RTL Design Engineer focused on Static Timing Analysis for its San Jose design team. You will translate microarchitectural specs into synthesizable RTL and collaborate with verification, physical design, DFT, firmware, systems, and validation teams to ensure successful tapeout and silicon validation.

You will work on high-performance connectivity ASICs, contribute to timing closure, power optimization, and implementation flows, and help drive robust RTL quality