Digital Design Engineer – DFT & ASIC/SoC Specialist

Analog Devices, Inc.; Dallas, Northern (TX, KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Analog Devices, Inc. is seeking a Digital Design Engineer focused on DFT who will define and implement DFT architectures for ASIC/SoC projects. You will insert scan chains, run ATPG, and verify designs analytically and with simulations.

Collaboration with multiple teams is essential to deliver high-coverage, low-power, and low-test-time patterns. The role requires a Masters in EE/CE and at least 2 years of DFT experience, with proficiency in scripting and experience with Tessent tools.

Qualifications

• MS degree in Electrical/Computer Engineering or similar.
• 2 years of directly related ASIC/SoC DFT experience.
• Strong understanding of DFT architecture and planning.
• Hands-on scan insertion and ATPG tool experience.
• Hands-on experience with DFT compression insertion, on-chip clock control insertion.
• Gate-level simulation with zero delay and SDF.
• Good understanding of failure analysis.
• Scripting: Perl/Python/Tcl.
• Team-player with strong communication skills.

Responsibilities

• Define and implement DFT architectures and specifications.
• Support DFT insertion across multiple product lines.
• Develop high-coverage, low-power, and low-test-time scan patterns.
• Conduct pre/post-silicon verification and debugging.
• Collaborate with peer organizations to integrate DFT solutions.

Skills

DFT design

ATPG tools

Perl/Python/Tcl

Gate-level simulation

Team collaboration

Communication skills

IEEE 1149/JTAG knowledge

Education

MS in Electrical/Computer Engineering

Tools

Tessent DFT tools

Job description

Analog Devices, Inc. is seeking a Digital Design Engineer focused on DFT who will define and implement DFT architectures for ASIC/SoC projects. You will insert scan chains, run ATPG, and verify designs analytically and with simulations.

Collaboration with multiple teams is essential to deliver high-coverage, low-power, and low-test-time patterns. The role requires a Masters in EE/CE and at least 2 years of DFT experience, with proficiency in scripting and experience with Tessent tools.