Digital Design Engineer, DFT

Hardware FYI; Dallas, Northern (TX, KY); Hybrid; USD 110,000 - 160,000; Full time

Job summary

Analog Devices, Inc., a global semiconductor leader, is seeking an experienced ASIC/SoC DFT engineer to drive DFT specifications, architecture, and implementation across product lines. The role emphasizes scalable scan patterns and early verification.

You will collaborate with cross-functional teams to push high-coverage, low-power designs, perform pre/post-silicon verification and debugging, and contribute to a fast-paced, team-oriented environment.

Qualifications

• Master's degree in EE/CE or equivalent.
• 2 years of ASIC/SoC DFT experience.
• Knowledge of DFT architecture and planning.
• Hands-on scan insertion and ATPG tool experience.
• Gate-level simulation with zero delay and SDF.

Responsibilities

• DFT specifications, architecture and implementation using state-of-the-art methodologies.
• Support various product lines for DFT insertion and for high coverage, low power, low test time scan patterns.
• Pre/Post silicon verification and debugging.
• Work independently as well as in a team.

Skills

DFT architecture

ATPG Tool experience

Perl/Python/Tcl scripting

Team-player

Strong written and verbal comms

Education

Master's degree in Electrical Engineering or Computer Engineering or similar

Tools

Tessent DFT tools

Gate-level simulation tools

IEEE 1149/JTAG

Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

As a key member of the team, he/she will be responsible for:

• DFT specifications, architecture and implementation using state-of-the-art methodologies and tools
• Support various product lines for DFT insertion
• Support various product lines for High Coverage, Low Power, Low Test Time scan patterns
• Pre/Post silicon verification & debug
• Work independently as well as in team

Minimum Qualifications

• Masters of Science degree in Electrical Engineering, Computer Engineering or similar
• 2 years of directly related experience in ASIC/SoC DFT
• Good understanding of DFT architecture and planning
• Hands on scan insertion and ATPG Tool experience
• Hands on experience of DFT Compression Insertion, On-Chip Clock Control Insertion
• Hands on experience of Gate-level simulation with zero delay and SDF
• Good understanding of Failure Analysis
• Scripting: Perl/Python/Tcl
• Team-player: the ability to forge and maintain relationships with peer-organizations
• Strong written and verbal communication skills

Preferred Qualifications

• Experience with Tessent DFT tools
• Good understanding of IEEE 1149 and JTAG
• Experience with LBIST and MBIST
• Experience with advanced DFT technologies like low power, SSN, Fault Grading.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days