Full-Chip Timing & SDC Engineer

Mirafra Technologies; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Mirafra Technologies is seeking a design lead to oversee fullchip SDCs and collaborate with physical design and DFT teams to close timing across multiple timing modes.

The role emphasizes developing methods to promote block level SDCs to fullchip, integrating fullchip changes back to block level, and ensuring SDC quality early in the design cycle; mentoring RTL owners and steering fullchip clocking design.

Qualifications

• Experience in Static Timing Analysis.
• Experience with constraint analyzer tools such as Fishtail/TCM and CCD.
• Experience with Spyglass CDC and glitch analysis.

Responsibilities

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Leading the fullchip clocking design including diagrams and related documentation.

Skills

Static Timing Analysis

Tools

Fishtail

TCM

CCD

Spyglass CDC

Job description

Mirafra Technologies is seeking a design lead to oversee fullchip SDCs and collaborate with physical design and DFT teams to close timing across multiple timing modes.

The role emphasizes developing methods to promote block level SDCs to fullchip, integrating fullchip changes back to block level, and ensuring SDC quality early in the design cycle; mentoring RTL owners and steering fullchip clocking design.