DFT Engineer for AI/ML ASICs

Tenstorrent; Austin (TX); Hybrid; USD 100,000 - 500,000; Full time

Benefits offered by this job

Equal opportunity employer

Competitive compensation package

Job summary

Tenstorrent is seeking a Design for Test (DFT) engineer to drive DFT features across RTL and IPs, from early design to tapeout. You will own ATPG and gate-level verification, coordinate with Test Engineering, and refine DFx flows that balance coverage with cost and intrusiveness.

The role supports hybrid work in the US, with opportunities at multiple sites. We welcome engineers at various experience levels, and offers align with level and location.

Qualifications

• 5+ years of industry experience in advanced DFx/DFT for complex ASIC/SoC designs.
• Fluent in Verilog RTL for DFT logic (lock-up latches, clock gates, scan anchors) and comfortable with SystemVerilog/UVM.
• Hands-on experience with ATPG and DFx insertion tools, fault models (Stuck-at, Transition, Path Delay, IDDQ, Cell-Aware), and low-power design flows.
• Strong debug and problem-solving skills across design hierarchies and collaboration with design, PD, verification, and test teams.

Responsibilities

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

Skills

Verilog RTL

SystemVerilog/UVM

ATPG

DFx tools

fault models

low-power design

debug skills

cross-functional collaboration

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

Synopsys VCS

Synopsys Verdi

Job description

Tenstorrent is seeking a Design for Test (DFT) engineer to drive DFT features across RTL and IPs, from early design to tapeout. You will own ATPG and gate-level verification, coordinate with Test Engineering, and refine DFx flows that balance coverage with cost and intrusiveness.

The role supports hybrid work in the US, with opportunities at multiple sites. We welcome engineers at various experience levels, and offers align with level and location.