DFT Engineer

Jobtailor; Austin (TX); On-site; USD 110,000 - 150,000; Full time

Job summary

Jobtailor in Austin, TX seeks an ASIC DFT Engineer to help define, implement, and review DFT features within a collaborative team.

You will generate, insert, and verify Memory BIST logic, perform scan insertion and ATPG pattern generation, and support silicon bringup on ATE. A strong background in EDA tools and MBIST verification is required.

The ideal candidate holds an MSEE or BS with relevant experience, and can contribute to timing and equivalence checking constraints and test cost analysis.

Qualifications

• MSEE with 2+ years of experience or BS with relevant industry experience.
• Possess strong hands on working knowledge on ASIC DFT design and verification.
• Experience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc.

Responsibilities

• Work within a collaborative team environment to define, implement, and review DFT features.
• Generate, insert, and verify Memory BIST logic.
• Perform scan insertion and ATPG pattern generation.
• Help develop and review DFT timing and equivalence checking constraints.
• Perform MBIST and ATPG pattern verification with gate level simulations.
• Identify and improve any test coverage gaps.
• Perform test cost planning and analysis.
• Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.

Skills

DFT features

Memory BIST logic

scan insertion

ATPG pattern generation

timing constraints

equivalence checking

MBIST verification

gate level simulations

test coverage analysis

test cost planning

Education

MSEE

BS in relevant field

Tools

FastScan

TestKompress

TetraMAX

Test Compiler

Job description

• Work within a collaborative team environment to define, implement, and review DFT features.
• You will generate, insert, and verify Memory BIST logic.
• Perform scan insertion and ATPG pattern generation.
• Help develop and review DFT timing and equivalence checking constraints.
• Perform MBIST and ATPG pattern verification with gate level simulations.
• Identify and improve any test coverage gaps.
• Perform test cost planning and analysis.
• Deliver MBIST and ATPG patterns to the product test group and support silicon bringup on the ATE.

Requirements

• MSEE with 2+ years of experience or BS with relevant industry experience.
• Possess strong hands on working knowledge on ASIC DFT design and verification.
• Experience in industry standard EDA tools for DFT such as FastScan, TestKompress, TetraMAX, Test Compiler etc.

Hard Skills

• DFT features
• Memory BIST logic
• scan insertion
• ATPG pattern generation
• timing constraints
• equivalence checking
• MBIST verification
• gate level simulations
• test coverage analysis
• test cost planning

Soft Skills

• collaborative teamwork

Certifications & Qualifications

• MSEE
• BS in relevant field