DFT Architect

TYLsemi; United States; Remote; USD 150,000 - 210,000; Full time

Job summary

TYLsemi is seeking an experienced DFT Architect to lead the design-for-test strategy and architecture for complex ASIC/SOC designs. You will drive end-to-end DFT across scan, MBIST, compression, boundary scan, and at-speed test methodologies with cross-functional teams to achieve high test coverage and successful silicon bring-up.

You will define SOC-level DFT architecture, mentor engineers, and develop automation flows that scale across advanced technology nodes.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 10+ years of experience in ASIC/SOC DFT implementation and architecture.
• Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies.
• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
• Strong understanding of RTL design, timing, physical design constraints, and silicon debug.
• Experience with advanced technology nodes and large SOC integration.
• Strong scripting and automation skills using Tcl, Python, Perl, or Shell.
• Excellent leadership, problem-solving, and cross-functional collaboration skills.

Responsibilities

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
• Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies.
• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
• Analyze and resolve DFT-related timing, routing, and testability challenges.
• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.
• Mentor junior engineers and provide technical leadership across projects.

Skills

DFT leadership

Cross-functional collaboration

Problem solving

Scripting (Tcl/Python)

Mentoring

Education

Bachelor’s/Master’s degree in Electronics, Electrical Engineering, or VLSI

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

JTAG

LBIST/MBIST

ATPG

Scan insertion

Job description

About the role

We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive end-to-end DFT architecture including scan, MBIST, compression, boundary scan, and at-speed test methodologies while collaborating with cross-functional teams to achieve high test coverage, quality, and silicon bring-up success.

What you’ll do

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.

• Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies.

• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.

• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.

• Analyze and resolve DFT-related timing, routing, and testability challenges.

• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.

• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.

• Mentor junior engineers and provide technical leadership across projects.

What We’re Looking For

• Bachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field.

• 10+ years of experience in ASIC/SOC DFT implementation and architecture.

• Strongexpertisein scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies.

• Hands-on experience with industry-standard DFT tools such as SiemensTessent, Synopsys DFT Compiler/TestMAX, or equivalent.

• Strong understanding of RTL design, timing, physical design constraints, and silicon debug.

• Experience with advanced technology nodes and large SOC integration.

• Strong scripting and automation skills usingTcl, Python, Perl, or Shell.

• Excellent leadership, problem-solving, and cross-functional collaboration skills.

Good to Have

• Experience with automotive safety standards such as ISO 26262.

• Exposure to chiplet-based architectures and 3D IC testing methodologies.

• Knowledge of diagnosis-driven yield improvement and silicon analytics.

Success in This Role Looks Like

• Delivery of robust DFT architectures with high test coverage and efficient manufacturing test cost.

• Successful silicon bring-up with minimal DFT-related issues.

• Improved DFTmethodologyscalability, automation, and execution efficiency.

• Strong technical leadership and contribution to organization-wide DFT best practices.