DFT & ASIC/SoC Design Engineer

Analog Devices, Inc.; Town of Texas (WI); On-site; USD 95,000 - 130,000; Full time

Job summary

Analog Devices, Inc. in Wisconsin is seeking an experienced DFT Engineer to contribute to specifications, architecture and implementation of advanced scan/ATP G methods across ASIC/SoC projects.

You will support DFT insertion for multiple product lines, participate in high-coverage, low-power scan patterns, and perform pre/post-silicon verification and debugging while collaborating with cross-functional teams to deliver robust testability.

Qualifications

• Masters of Science degree in Electrical Engineering, Computer Engineering or similar.
• 2 years of directly related experience in ASIC/SoC DFT.
• Good understanding of DFT architecture and planning.
• Hands on scan insertion and ATPG Tool experience.
• Hands on experience of DFT Compression Insertion, On-Chip Clock Control Insertion.
• Hands on experience of Gate-level simulation with zero delay and SDF.
• Good understanding of Failure Analysis.
• Scripting: Perl/Python/Tcl
• Team-player: the ability to forge and maintain relationships with peer-organizations
• Strong written and verbal communication skills.

Responsibilities

• DFT specifications, architecture and implementation using state-of-the-art methodologies and tools
• Support various product lines for DFT insertion
• Support various product lines for High Coverage, Low Power, Low Test Time scan patterns
• Pre/Post silicon verification & debug
• Work independently as well as in team

Skills

DFT knowledge

ATPG/DFT tooling experience

Team player

Strong communication skills

Scripting (Python/Perl/Tcl)

Gate-level simulation

Education

Master of Science in Electrical Engineering or Computer Engineering

Tools

Tessent DFT tools

LBIST/MBIST

IEEE 1149.1/JTAG

Job description

Analog Devices, Inc. in Wisconsin is seeking an experienced DFT Engineer to contribute to specifications, architecture and implementation of advanced scan/ATP G methods across ASIC/SoC projects.

You will support DFT insertion for multiple product lines, participate in high-coverage, low-power scan patterns, and perform pre/post-silicon verification and debugging while collaborating with cross-functional teams to deliver robust testability.