A leading technology company in Austin, Texas, is seeking motivated interns for their Mixed-Signal Verification Engineering team. This internship offers a chance to collaborate with engineers on verification for mixed-signal products. Candidates should be pursuing a MS or PhD in Electrical Engineering, with expertise in Hardware Description Languages like Verilog or VHDL. Interns are expected to work in-office up to 5 days a week. This role presents an excellent opportunity to gain hands-on experience in a dynamic work environment.
Qualifications
Currently pursuing a MS or PhD in Electrical Engineering or a related field.
Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL.
Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM, Vera, or others.
Solid understanding of digital design fundamentals and verification methodologies.
Responsibilities
Assist in verification planning and strategy development.
Support testbench creation, maintenance, and enhancement.
Contribute to failure analysis, debug, and resolution efforts.
Help with coverage analysis and population for thorough verification.
Work on digital/mixed-signal modeling, test generation, and verification flow.
Skills
Hardware Description Languages (HDLs)
SystemVerilog/UVM
Verilog
VHDL
Education
MS or PhD in Electrical Engineering or related field
Job description
A leading technology company in Austin, Texas, is seeking motivated interns for their Mixed-Signal Verification Engineering team. This internship offers a chance to collaborate with engineers on verification for mixed-signal products. Candidates should be pursuing a MS or PhD in Electrical Engineering, with expertise in Hardware Description Languages like Verilog or VHDL. Interns are expected to work in-office up to 5 days a week. This role presents an excellent opportunity to gain hands-on experience in a dynamic work environment.