Design Verification Intern - Mixed-Signal & Debug

Cirrus Logic; Chandler (AZ); Hybrid; USD 34,000 - 48,000; Full time

Job summary

Cirrus Logic is seeking highly motivated interns for the Mixed-Signal Verification Engineering team in Chandler, AZ for Fall 2026, a 12-week full-time internship. You will collaborate with digital and analog designers, applications engineers, and manufacturing test teams to verify products pre- and post-silicon.

Ideal candidates are pursuing an MS or PhD in Electrical Engineering with strong Verilog/VHDL and SystemVerilog/UVM familiarity, and a solid understanding of digital design concepts.

Qualifications

• Pursuing MS or PhD in Electrical Engineering.
• Strong HDL background in Verilog or VHDL.
• Familiarity with HVLs like SystemVerilog/UVM and Vera.

Responsibilities

• Assist in verification planning and strategy development.
• Support testbench creation, maintenance, and enhancement.
• Contribute to failure analysis, debug, and resolution efforts.
• Help with coverage analysis and population to ensure robust verification.
• Work on digital/mixed-signal modeling, test generation, and flow development.

Skills

Verilog

VHDL

SystemVerilog/UVM

Vera

Education

MS or PhD in Electrical Engineering

Job description

Cirrus Logic is seeking highly motivated interns for the Mixed-Signal Verification Engineering team in Chandler, AZ for Fall 2026, a 12-week full-time internship. You will collaborate with digital and analog designers, applications engineers, and manufacturing test teams to verify products pre- and post-silicon.

Ideal candidates are pursuing an MS or PhD in Electrical Engineering with strong Verilog/VHDL and SystemVerilog/UVM familiarity, and a solid understanding of digital design concepts.