Mixed-Signal Verification Intern

Cirrus Logic, Inc.; Chandler (AZ); Hybrid; USD 33,480 - 44,640; Full time

Job summary

Cirrus Logic, Inc. is looking for motivated interns to join the Mixed-Signal Verification Engineering team in Chandler, Arizona for the Fall 2026 semester. This full-time internship involves working closely with digital and analog designers to support verification efforts on mixed-signal products. Interns should be pursuing a MS or PhD in Electrical Engineering, with a strong background in HDLs like Verilog and a good understanding of digital design. The role requires a hybrid work schedule, with potential in-office work up to 5 days a week.

Qualifications

• Currently pursuing a MS or PhD in Electrical Engineering or a related field.
• Strong background in Hardware Description Languages (HDLs) such as Verilog or VHDL.
• Familiarity with Hardware Verification Languages (HVLs) like SystemVerilog/UVM.
• Solid understanding of digital design fundamentals and verification methodologies.

Responsibilities

• Assist in verification planning and strategy development.
• Support testbench creation, maintenance, and enhancement.
• Contribute to failure analysis, debug, and resolution efforts.
• Help with coverage analysis and population for thorough verification.
• Work on digital/mixed-signal modeling and verification flow development.

Skills

Hardware Description Languages (HDLs) such as Verilog or VHDL

Hardware Verification Languages (HVLs) like SystemVerilog/UVM

Digital design fundamentals and verification methodologies

Education

Currently pursuing a MS or PhD in Electrical Engineering or a related field

Job description

Cirrus Logic, Inc. is looking for motivated interns to join the Mixed-Signal Verification Engineering team in Chandler, Arizona for the Fall 2026 semester. This full-time internship involves working closely with digital and analog designers to support verification efforts on mixed-signal products. Interns should be pursuing a MS or PhD in Electrical Engineering, with a strong background in HDLs like Verilog and a good understanding of digital design. The role requires a hybrid work schedule, with potential in-office work up to 5 days a week.