Application Specific Integrated Circuit Verification Engineer

CBL Solutions; United States; Remote; USD 120.000 - 170.000; Vollzeit

Zusammenfassung

CBL Solutions is seeking an ASIC Verification Engineer focused on UVM and GLS to join a remote-friendly team. You will lead verification of complex ASIC/SoC blocks, designing verification components and sign-off criteria in a zero-defect mindset.

Your remit includes building UVM environments from scratch, executing GLS with timing analyses, and driving regression automation. Remote work is acceptable, with the engagement lasting 12+ months.

Qualifikationen

• Experience building complete UVM verification environments from scratch.
• Extensive gate-level simulation (GLS) with SDF annotation and timing validation.
• Expert-level proficiency in SystemVerilog and UVM for ASIC/SoC verification.
• Preferred knowledge of Ethernet, PCIe, or UCIe protocols.

Aufgaben

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.
• Develop UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.
• Execute and debug GLS, including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.
• Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.

Kenntnisse

UVM verification

GLS experience

SystemVerilog

Testbench architecture

Jobbeschreibung

Our client is looking for an ASIC Verification Engineer (UVM & GLS Focus),

Location: Remote is fine

Duration: 12+ Months

Must-Have Skills

• Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.
• Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation failures.
• Expert-level proficiency in SystemVerilog and UVM for complex ASIC/SoC verification.
• Protocol knowledge in Ethernet, PCIe, or UCIe is preferred but secondary to strong UVM and GLS expertise.

Key Responsibilities

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.
• Develop and maintain UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.
• Execute and debug Gate-Level Simulations (GLS), including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.
• Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.

Required Qualifications

• Proven experience building complete UVM verification environments from scratch.