Design verification Engineer- Sunnyvale, CA

Cystems Logic Inc; Santa Clara (CA); Presencial; USD 100 000 - 140 000; Tempo parcial

Resumo da oferta

Cystems Logic Inc in Sunnyvale, CA seeks an experienced Design Verification Engineer (UVM) to develop and maintain reusable verification environments for complex semiconductor designs.

You will write constrained-random and directed tests in SystemVerilog, build UVM components, write SVA assertions, and drive coverage closure toward sign-off.

Qualificações

• UVM-based verification experience required.
• Strong SystemVerilog programming skills.
• Hands-on testbench development experience.
• Experience with coverage closure and scoreboarding.

Responsabilidades

• Develop and maintain reusable UVM-based verification environments.
• Create and implement test plans, test scenarios, and verification strategies.
• Develop constrained-random and directed test cases using SystemVerilog.
• Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.
• Develop assertions using SystemVerilog Assertions (SVA).
• Perform functional, code, and assertion coverage analysis.
• Debug simulation failures and identify design or testbench issues.
• Work closely with RTL designers and architecture teams to understand design specifications.
• Drive functional coverage closure and sign-off.
• Participate in design reviews, verification planning, and regression analysis.
• Automate verification tasks using scripting languages such as Python, Perl, or Shell.

Conhecimentos

UVM-based verification

SystemVerilog

Constrained-random tests

Testbench development

Debugging & coverage

OOP concepts

Ferramentas

Synopsys VCS

Cadence Xcelium

Descrição da oferta de emprego

Design verification Engineer- Sunnyvale, CA

• Contract

Hi,

Job Title: Design Verification Engineer (UVM)

Location: Sunnyvale, CA

Mandatory Skill: Strong hands-on UVM expertise is a MUST.

Job Summary: We are looking for an experienced Design Verification Engineer with strong expertise in SystemVerilog and UVM (Universal Verification Methodology) to develop and execute verification environments for complex semiconductor designs. The ideal candidate should have hands-on experience in functional verification, testbench development, debugging, and coverage closure.

Key Responsibilities :

Develop and maintain reusable UVM-based verification environments.

Create and implement test plans, test scenarios, and verification strategies.

Develop constrained-random and directed test cases using SystemVerilog.

Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.

Develop assertions using SystemVerilog Assertions (SVA).

Perform functional, code, and assertion coverage analysis.

Debug simulation failures and identify design or testbench issues.

Work closely with RTL designers and architecture teams to understand design specifications.

Drive functional coverage closure and achieve verification sign-off.

Participate in design reviews, verification planning, and regression analysis.

Automate verification tasks using scripting languages such as Python, Perl, or Shell.

Required Skills

Strong hands-on experience in UVM-based functional verification.

Excellent knowledge of SystemVerilog.

Experience developing reusable UVM testbenches from scratch.

Strong understanding of OOP concepts and constrained-random verification.

Experience with UVM sequences, sequencers, drivers, monitors, agents, and scoreboards.

Hands-on experience with SystemVerilog Assertions (SVA).

Knowledge of functional coverage and code coverage.

Experience with simulation and debugging tools such as:

Synopsys VCS

Cadence Xcelium

Strong debugging and problem-solving skills.

Good understanding of digital design concepts and RTL verification methodologies.

All your information will be kept confidential according to EEO guidelines.