Design Verification Engineer

Apple Inc.; Los Angeles (CA); On-site; USD 120,300 - 210,100; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Employee stock purchase plan

Educational reimbursement

Discretionary bonuses

Job summary

A leading technology company in Los Angeles is seeking a skilled design verification engineer to ensure bug-free first silicon for its products. The successful candidate will be responsible for developing verification methodology, test plans, and environments. Required qualifications include a bachelor's degree and deep knowledge of SystemVerilog and UVM. Preferred candidates will have 3+ years experience and familiarity with verification methodologies, simulators, and serial protocols. Compensation ranges from $120,300 to $210,100 with various benefits.

Qualifications

• Minimum of a bachelor's degree.
• 3+ years of relevant industry experience or equivalent strongly preferred.
• Deep knowledge of SystemVerilog and UVM.

Responsibilities

• Study design specifications and create test plans.
• Develop infrastructure in SystemVerilog/UVM.
• Develop and fix failures from regressions.

Skills

SystemVerilog

UVM

Python

C/C++

PCIe

USB

DDR

Education

Bachelor's degree in a technical subject area

BS degree preferred

Tools

Verification methodologies

Simulators

Waveform viewers

Job description

At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for a digital-focused DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test‑plan development, verification environment development including stimulus and checkers, test‑writing, debug, coverage, sign‑off for RTL freeze and tape‑out.

Description

In this role, you will be responsible for ensuring bug‑free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro‑architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring‑up, DV environment bring‑up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test‑benches, track and report DV progress using a variety of metrics, including bugs and coverage.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Minimum Qualifications

• Minimum requirement of a bachelors degree

Preferred Qualifications

• BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent strongly preferred
• Deep knowledge of SystemVerilog and UVM
• Deep knowledge in developing scalable and portable test‑benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewers
• Build and run automation, coverage collection, gate level simulations
• Some UVM knowledge, C/C++ level knowledge
• Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
• Basic knowledge of formal verification methodology
• Some experience with power‑aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL

Compensation and Benefits

Base pay range: $120,300 to $210,100. Pay depends on skills, qualifications, experience, and location.

Apple employees also have the opportunity to become Apple shareholders through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. Additionally, you’ll receive benefits including comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, reimbursement for educational expenses (including tuition), and the possibility of discretionary bonuses, commissions, and relocation assistance.

Equal Opportunity

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.