ASIC Verification Engineer — High-Speed DV & Formal

Avicena Tech; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You will develop robust verification environments, using UVM, SystemVerilog, and Python scripting, to ensure functionally correct, high-performance digital ICs for silicon photonics and optical interconnect solutions.

The ideal candidate has 3+ years of ASIC/SoC DV experience, strong debugging skills, and a track record of regression and coverage closure.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or related field.
• 3+ years of professional ASIC/SoC design verification experience.
• Strong proficiency with SystemVerilog and UVM-based verification environments.
• Experience with Python or Perl scripting for automation.

Responsibilities

• Develop comprehensive verification environments and testbenches using advanced methodologies like UVM.
• Define and execute verification plans with feature lists, test strategies, and coverage goals.
• Create constrained-random, directed, and stress tests and coverage models.
• Analyze results, debug complex failures, and drive root-cause resolution with design engineers.
• Drive coverage closure and manage regression suites for efficiency.
• Apply formal verification techniques for key design properties, e.g., CDC and state machines.
• Develop automation scripts (Python/Perl) to enhance verification flow.

Skills

UVM verification

SystemVerilog

Python scripting

Debugging skills

Education

Bachelor's or Master's in EE/ECE

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You will develop robust verification environments, using UVM, SystemVerilog, and Python scripting, to ensure functionally correct, high-performance digital ICs for silicon photonics and optical interconnect solutions.

The ideal candidate has 3+ years of ASIC/SoC DV experience, strong debugging skills, and a track record of regression and coverage closure.