Design Verification Engineer

Eximietas Design; San Jose (CA); On-site; USD 133,000 - 187,000; Full time

Job summary

An established industry player is looking for a Senior SOC Design Verification Engineer to join their innovative team. With a focus on cutting-edge System-on-Chip designs, you will lead verification efforts and develop comprehensive strategies for high-speed SOCs. This role offers the opportunity to collaborate with cross-functional teams, mentor junior engineers, and ensure the robustness of designs through rigorous testing. If you have a passion for technology and a commitment to excellence, this is your chance to make a significant impact in a dynamic environment.

Qualifications

• 15+ years of experience in SOC Design Verification.
• Expertise in UVM and System Verilog required.
• Hands-on experience with high-speed protocols like PCIe and Ethernet.

Responsibilities

• Lead SOC Design Verification efforts for complex projects.
• Develop comprehensive verification strategies and test plans.
• Mentor junior verification engineers and manage a dynamic team.

Skills

SOC Design Verification

UVM

System Verilog

Verification Tools (VCS, Xsim)

Scripting (Shell, Makefile, Perl)

Gate-level simulations

Power-aware verification

Problem-solving

Education

Bachelor's degree in Computer Science or Electrical Engineering

Master's degree in Computer Science or Electrical Engineering

PhD in Computer Science or Electrical Engineering

Tools

VCS

Xsim

Waveform analysers

Synopsys VIPs

Cadence VIPs

Job description

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We are seeking experienced and highly skilled Senior SOC Design Verification Engineers with a minimum of 15 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System-on-Chip designs.

Location: Bay Area, CA

Job Description:

• Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.
• Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM
• Conduct Gate-level simulations and power-aware verification using Xprop and UPF.
• Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.
• Analyze and implement System Verilog assertions and coverage (code, toggle, functional).
• Provide mentorship and technical guidance to junior verification engineers.
• Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.
• Ensure verification signoff criteria are met and documentation is comprehensive.
• Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.
• Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.
• Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.

Qualifications:

• Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.
• 15+ years of hands-on experience in SOC Design Verification.
• Expertise in UVM (Universal Verification Methodology) and System Verilog.
• Prior experience working on IP level and SOC level verification projects.
• Proficient in verification tools such as VCS, Xsim, waveform analysers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).
• Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.
• Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.
• Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.
• Proficiency in scripting languages such as shell, Makefile, and Perl.
• Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.
• C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Feel free to reach out to [e-mail] for resumes, referrals, or discussions.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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