Design Verification Engineer

Avila IT; Fremont (CA); On-site; USD 110,000 - 170,000; Full time

Job summary

Avila IT in Fremont, CA is seeking a digital design verification engineer to translate design requirements into verification strategies and to develop testbenches and automated coverage.

You will collaborate with design and validation teams to investigate failures and improve confidence, applying SystemVerilog or UVM and disciplined debugging.

Qualifications

• Experience with digital design verification concepts and disciplined debugging.
• Knowledge of simulation tools and verification methodologies is expected.

Responsibilities

• Translate design requirements into verification strategies and test cases.
• Develop testbenches, assertions, and automation for repeatable coverage.
• Work with design and validation teams to investigate failures and improve confidence.

Skills

Digital design verification

SystemVerilog

UVM

Testbench development

Debugging

Job description

Build verification plans and test systems that catch problems before a design or release moves forward.

What you will work on

• Translate design requirements into verification strategies and test cases.
• Develop testbenches, assertions, and automation for repeatable coverage.
• Work with design and validation teams to investigate failures and improve confidence.

What helps you thrive

Experience with digital design verification concepts, simulation, SystemVerilog or UVM, and disciplined debugging. Share the relevant tools and projects in your application.

How the work happens

Work directly with a team on practical engineering problems. Discuss engagement scope and working arrangements with our team.

Build carefully. Stay close to the problem. Make the result understandable to the people who use it.

Bring us a workflow, an existing system, or a team that needs hands-on engineering support.