Customer Engagement Engineer II

Cadence Design Systems; San Jose (CA); Hybrid; USD 105,000 - 195,000; Full time

Job summary

Cadence Design Systems in San Jose seeks a Customer Engagement Engineer II to work with customers, field AEs, and R&D to provide top-tier technical support for Palladium, Protium, and PDAPP products. You will manage cases, reproduce issues with test cases, and coordinate with R&D to validate fixes.

The role requires a BS-EE/CE with 1+ year experience, strong HDL knowledge, and familiarity with Unix scripting. Occasional travel may be needed; salary ranges are competitive for California.

Qualifications

• BS-EE/CE with 1+ year experience in design/verification or applications engineering.
• Strong knowledge of HDL and verification methods for complex designs.
• Proficient in Verilog, SystemVerilog, and VHDL.

Responsibilities

• Handle incoming SFDC cases reported by field AEs and customers.
• Report tool bugs to R&D and collect collaterals/testcases.
• Test R&D fixes/patches.
• Track customer metrics in JIRA and generate quality reports for management.
• Occasional travel may be required to resolve critical issues.

Skills

Verilog

SystemVerilog

VHDL

HDL debugging

Unix/Linux scripting

UVM

PCIe/USB/Ethernet

Test case creation

Emulation

Communication skills

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

SFDC (Salesforce)

JIRA

Cadence Palladium Emulation

Job description

## Customer Engagement Engineer IIApply: SAN JOSE: Full time: Posted Today: End Date: December 31, 2026 (30+ days left to apply): R56482## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**As an integral member of the HSV Customer Support Team, you will work with our customers and field AE teams and R&D groups to provide technical support for our Palladium, Protium and Virtual Protocol (PDAPP) products. You will enjoy the experience and challenge in working with a broad spectrum of designs and customers. **Responsibilities includes:*** Handling incoming SFDC cases reported by field AEs and customers.* Report any tool bugs to R&D and work with field AE and customer to collect necessary collaterals and/or testcases.* Test R&D fixes/patches.* Tracking customer metrics in JIRA system, generating quality report for management.* undefined**Position Requirements:**Requires a BS-EE/CE (MS-EE/CE preferred) with a minimum of 1 years experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.General knowledge of design debug techniques and a strong understanding in logic design.General knowledge in verification methodologies for complex EDA environments.Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.Proficiency in Unix/Linux scripting languages (ksh/bash/csh).Experience with emulation, Cadence's Palladium product preferred.General knowledge in TBA, SVA, SV coverage, Low Power(UPF). UVM experience is a plus.General knowledge in PCIe, USB and Ethernet protocol.Excellent communication skills. Must have ability to communicate complex issues to internal teams and customers in a clear and concise manner.Occasional travel may be required to resolve critical customer issues.undefined*The annual salary range for California is $105,000 to $195,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*