Principal Design Engineer

Cadence

San Jose (CA)

On-site

USD 140,000 - 260,000

Full time

25 hours ago
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Job summary

Cadence in California is seeking an experienced hardware/SoC design leader to guide a team developing next‑generation subsystems. You will oversee RTL synthesis, floor planning, clock-tree optimization, and physical verification across Front End RTL and Back End teams.

The role requires strong expertise with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and deep knowledge of 5nm/3nm/2nm processes, Linux scripting, and standard interfaces (PCIe, DDR, LPDDR, SRAM, UCIe).

Qualifications

  • Experience with Cadence tools: Innovus, Tempus, QRC, Voltus and Pegasus.
  • Experience with advanced technologies like 5nm, 3nm and 2nm nodes.
  • Proficiency with Linux servers; scripting with Shell/Perl/TCL.
  • Knowledge of PCI Express, DDR, LPDDR, SRAM, UCIe interfaces.

Responsibilities

  • Lead a team to implement SOCs or subsystem chips.
  • Work on RTL synthesis and floor planning.
  • Build clock trees and perform optimizations.
  • Close timing, IR drop and physical verification.
  • Review and document designs for taping out.
  • Interface with Front End RTL design teams and Back End verification teams.

Skills

SOC design leadership
RTL synthesis
Floor planning
Timing closure
Physical verification
Team coordination

Education

BS in Electrical Engineering (minimum 7 years)
MS in Electrical Engineering (minimum 5 years)
PhD in Electrical Engineering (minimum 1 year)

Tools

Cadence Innovus
Cadence Tempus
Cadence QRC
Cadence Voltus
Cadence Pegasus

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage
  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
Job Responsibility
  • Lead a team to implement SOCs or sub system chips
  • Work on RTL synthesis and floor planning
  • Build clock trees and perform optimizations
  • Close timing, IR drop and physical verification
  • Review and Document designs for taping out
  • Interface with Front End RTL design teams and Back End verification teams
Position Requirements/Qualifications
  • BS in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum 1 year of experience
  • Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
  • Experience with advanced technologies like 5nm, 3ns and 2nm nodes
  • Experience using Linux servers, Script development using Shell/Perl/TCL
  • Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

The annual salary range for California is $140,000 to $260,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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