Custom Clock Design Architect – High-Perf CPU

Nuvacore; Santa Clara (CA); On-site; USD 140,000 - 250,000; Full time

Job summary

Nuvacore in Santa Clara, CA, is building a high-performance, low-power CPU. The Custom Clock Design and Distribution Engineer will architect and deliver clock generation and distribution networks that set frequency, skew, jitter, and power for the product.

You will collaborate across PLL/FLL, timing, power, CAD, physical design and DFT teams to ensure clock source models, jitter budgets, and power-aware clocking meet stringent PPA targets.

Qualifications

• BS or MS in EE/related field with 5+ years in clock design.
• Hands-on transistor-level clock design experience.
• Experience with H-tree/mesh/CTS and low-skew networks.
• Strong SPICE and signal-integrity knowledge.
• STA signoff across Functional and DFT modes.
• Tape-out and silicon-validated PPA experience.
• Excellent cross-team communication.

Responsibilities

• Architect end-to-end clock generation and distribution for high-frequency CPU cores.
• Design and characterize transistor-level clock circuits meeting PPA targets.
• Own clock-network closure with SPICE, EM/IR, jitter analysis, and signoff.
• Collaborate with PLL/FLL, timing, CAD, physical design, and DFT teams.

Skills

BS/MS clock design

5+ years IC clock design

Transistor-level design

Low-skew CTS

SPICE simulation

STA signoff

Tape-out PPA experience

Cross-team communication

Python/Perl/TCL

Education

Bachelor or Master in EE/related

Tools

Python

Perl

TCL

Job description

Nuvacore in Santa Clara, CA, is building a high-performance, low-power CPU. The Custom Clock Design and Distribution Engineer will architect and deliver clock generation and distribution networks that set frequency, skew, jitter, and power for the product.

You will collaborate across PLL/FLL, timing, power, CAD, physical design and DFT teams to ensure clock source models, jitter budgets, and power-aware clocking meet stringent PPA targets.