CPU Clock Design Engineer – Jitter, CTS & Low-Power Timing

Qualcomm; Santa Clara (CA); On-site; USD 142,200 - 213,400; Full time

Benefits offered by this job

Competitive bonus program

RSU grants

Job summary

Qualcomm in Santa Clara, CA is seeking a Physical Design Clock Engineer to collaborate with microarchitecture, RTL, CAD, block and top-level physical design teams to create best-in-class clocking solutions for next generation CPUs.

The role requires expertise in clock generation, jitter analysis, and low-skew/low-power design, with responsibilities spanning PLLs, CTS, and clock distribution methodology across CPU designs.

Qualifications

• BS/BE in EE/CE/CS with 2+ years hardware or MS with 1+ year; PhD also acceptable.
• Deep knowledge of clock generation, low skew, and low power design.
• Experience with PLL, jitter measurements, and clock distribution.

Responsibilities

• Perform jitter analysis and provide feedback to block/top level PD engineers on key fixes required.
• Understand, implement and validate CPU clocking with design teams.
• Drive clock generation and distribution methodology for CPU.
• Collaborate with CAD and block level designers to optimize skew and power.

Skills

Clock design

Jitter analysis

SPICE simulation

RTL CAD coordination

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree in Electrical Engineering

PhD in Electrical Engineering or related field

Tools

SPICE

CAD tools

Job description

Qualcomm in Santa Clara, CA is seeking a Physical Design Clock Engineer to collaborate with microarchitecture, RTL, CAD, block and top-level physical design teams to create best-in-class clocking solutions for next generation CPUs.

The role requires expertise in clock generation, jitter analysis, and low-skew/low-power design, with responsibilities spanning PLLs, CTS, and clock distribution methodology across CPU designs.