Lead CPU Custom Layout & Memory Architect

Nuvacore; Santa Clara (CA); In loco; USD 200.000 - 300.000; Tempo pieno

Descrizione del lavoro

Nuvacore is seeking a Custom Library and Memory Layout Lead to drive layout for high-performance CPU designs in Santa Clara. You will lead layout of custom library cells and memory arrays, own end-to-end closure, and collaborate with foundry, CAD, and circuit teams to ensure PPA targets are met.

You will define layout methodologies, build automation, and manage external vendors to scale layouts across macro designs.

Competenze

• BS or MS with 12+ years in custom/standard-cell and/or memory layout at advanced CMOS nodes.
• Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays.
• Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and LVSC closure using industry-standard EDA tools.
• Strong understanding of layout-dependent effects, matching, and symmetry techniques and impact on PPA.
• Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.

Mansioni

• Lead physical layout of custom library cells and memory arrays at advanced nodes.
• Own end-to-end layout closure: floorplanning, place-and-route, DRC/LVS cleanup, and extraction hand-off.
• Collaborate with circuit design, foundry, CAD, and DFT teams to optimize layout for PPA and yield.
• Define and drive layout automation and best practices, including script-based generation and regression flows.
• Manage layout vendors and contractors, scoping work, and reviewing deliverables for PPA and compliance.

Conoscenze

Layout engineering

PPA optimization

EDA collaboration

Automation scripting

Formazione

BS/MS in Electrical Engineering

Strumenti

Virtuoso

Calibre

StarRC

Descrizione del lavoro

Nuvacore is seeking a Custom Library and Memory Layout Lead to drive layout for high-performance CPU designs in Santa Clara. You will lead layout of custom library cells and memory arrays, own end-to-end closure, and collaborate with foundry, CAD, and circuit teams to ensure PPA targets are met.

You will define layout methodologies, build automation, and manage external vendors to scale layouts across macro designs.