Staff Clock Architect for High-Performance ASICs

QUALCOMM, Inc.; Austin (TX); On-site; USD 174,000 - 262,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a senior Clock Physical Design Engineer in Austin, TX. You will own clock PD methodology, implement advanced clock structures, and drive signoff across NSP ASIC/SoC designs.

The role requires 10+ years in ASIC/SoC physical design with hands-on experience in clock distribution, SPICE analysis, and multi-tool signoff. Collaboration across PD, timing, power, PLL, and CAD teams is essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC Physical Design with clock implementation and timing closure.
• Proven experience taking complex designs through physical design convergence and tapeout.

Responsibilities

• Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
• Architect, implement, and optimize advanced clock distribution structures (H-trees, mesh, spine, hierarchical distribution).
• Perform detailed SPICE simulation and transistor-level analysis of clock structures for waveform quality and robustness.
• Analyze clock-related timing, power, noise, and variation across operating conditions.
• Drive clock convergence and signoff across modes, corners, voltages, temperatures, and frequencies.
• Collaborate with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams on clock signoff.

Skills

Clock architecture

Timing closure

Power-aware design

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or related

Master's degree in Science/Engineering or related

PhD in Science/Engineering or related

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus

Synopsys PrimeTime

RC extraction tools

Job description

Qualcomm Technologies, Inc. is seeking a senior Clock Physical Design Engineer in Austin, TX. You will own clock PD methodology, implement advanced clock structures, and drive signoff across NSP ASIC/SoC designs.

The role requires 10+ years in ASIC/SoC physical design with hands-on experience in clock distribution, SPICE analysis, and multi-tool signoff. Collaboration across PD, timing, power, PLL, and CAD teams is essential.