CPU Verification Contract

IC Resources; California; Remote; USD 96,000 - 165,000; Full time

Job summary

IC Resources seeks a Design Verification Engineer for a contract role in Palo Alto, CA, with remote considerations. The engineer will own verification for SoC blocks and subsystems, from testbench architecture to coverage closure and signoff, collaborating with customer teams.

The role requires 6+ years of hands-on verification, SystemVerilog/UVM, and experience with PCIe/Ethernet. Remote work is considered, with onsite visits one week per month.

Qualifications

• 6+ years hands-on design verification experience.
• Multiple production tapeouts completed.
• Proficiency in SystemVerilog and UVM required.
• Experience with Arm CPU clusters, interconnects, PCIe and Ethernet.
• Strong debugging and verification skills.
• Ability to work independently in fast-paced environments.

Responsibilities

• Own verification plans, testbench architecture, and signoff.
• Develop SystemVerilog/UVM environments, sequences, scoreboards, and checkers.
• Verify PCIe, Ethernet, CPU integration, interconnects, and switches.
• Run regressions, track coverage, and debug failures.
• Set up verification flows for new programmes.
• Use AI-assisted tools for test generation, debug, and coverage closure.
• Work directly with customer design and verification teams.

Skills

SystemVerilog

UVM

Verification

Testbench development

Debugging

Independent work

Tools

JasperGold

AI-assisted verification tools

Emulation

Hardware-accelerated simulation

Job description

Design Verification Engineer – Contract

Palo Alto, California | Remote Considered | Contract

IC Resources is working with a stealth-mode startup semiconductor company developing next-generation silicon design tools using advanced AI systems.

This role will involve owning verification for SoC blocks and subsystems, from testbench architecture through to coverage closure and signoff, across real customer programmes.

You will be required to visit the site 1 week per month

Key Responsibilities

• Own verification plans, testbench architecture, and signoff


• Develop SystemVerilog/UVM environments, sequences, scoreboards, and checkers


• Verify PCIe, Ethernet, CPU integration, interconnects, and switches


• Run regressions, track coverage, and debug failures


• Set up verification flows for new programmes


• Use AI-assisted tools for test generation, debug, and coverage closure


• Work directly with customer design and verification teams

Key Experience Required

• 6+ years of hands-on Design Verification experience


• Multiple production tapeouts


• Strong SystemVerilog and UVM experience


• Experience with Arm CPU clusters, interconnects, PCIe, Ethernet, or CPU/subsystem integration


• Strong debugging and verification skills


• Ability to work independently in fast-paced environments

Desirable Experience

• Formal verification and SVA, Using JasperGold


• AMBA, PCIe, or Ethernet VIP


• Emulation or hardware-accelerated simulation


• Consulting or contract engineering experience


• AI-assisted verification tools