CPU Timing Design Engineer for Next-Gen SoCs

TSP talent; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

TSP talent is seeking a CPU Physical Design Timing Engineer responsible for delivering high-performance, low-power CPU blocks for next-generation wireless and mobile SoCs.

You will own timing closure, develop constraints, perform static timing analysis, implement ECOs, and sign-off across process corners while collaborating with RTL, architecture, and PD teams to optimize performance, power and area.

Experience with EDA tools and advanced process nodes is required.

Qualifications

• Experience with physical design timing, static timing analysis, and ECO techniques.
• Strong understanding of CPU design and implementation challenges.
• Proficiency with industry EDA tools and advanced process nodes.
• Excellent collaboration and problem-solving skills.

Responsibilities

• Owning timing closure for complex CPU components, including constraint development, static timing analysis, ECO implementation, and sign-off across multiple process corners.
• Collaborating closely with RTL, architecture, place-and-route, and PD teams to optimize performance, power, and area.
• Utilizing industry-standard EDA tools and advanced process nodes to resolve challenging timing issues.
• Contributing to methodology improvements, automation, and best practices within a fast-paced, collaborative environment.

Skills

Static timing analysis

Timing closure

Eco techniques

CPU design

Collaboration

Tools

EDA tools

Job description

TSP talent is seeking a CPU Physical Design Timing Engineer responsible for delivering high-performance, low-power CPU blocks for next-generation wireless and mobile SoCs.

You will own timing closure, develop constraints, perform static timing analysis, implement ECOs, and sign-off across process corners while collaborating with RTL, architecture, and PD teams to optimize performance, power and area.

Experience with EDA tools and advanced process nodes is required.