Senior Silicon Timing & Design Engineering Lead

Intel Corporation; Santa Clara (CA); Hybrid; USD 221,000 - 312,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel Corporation in Santa Clara is seeking a Physical Design Timing Engineer to ensure optimal timing, power efficiency, and performance of SoC designs. You will collaborate with cross-functional teams to develop advanced methodologies and drive timing solutions across chip blocks.

The role requires extensive experience in timing analysis, constraint generation, and clocking flows, with proficiency in TCL scripting, and a strong foundation in digital design and power-performance optimization.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• At least 12 years of experience with a Bachelor's degree, 8 years with a Master's, or 6 years with a PhD in timing analysis or physical design.
• Proficiency in static timing analysis, timing constraint generation, and timing optimization techniques.
• Experience with physical design timing tools and flows (TFM).
• Strong knowledge of SoC clocking and timing budgeting.
• Familiarity with TCL scripting for automation and design optimization.
• Understanding of digital design fundamentals and power/performance optimization.

Responsibilities

• Perform comprehensive timing analysis and optimization for high-performance designs.
• Generate and validate timing constraints and address timing violations at chip and block levels.
• Conduct timing rollups ensuring optimized performance and power characteristics.
• Develop timing models to enhance efficiency of the physical design team.
• Define PVT conditions for product operating plans and binning requirements.
• Collaborate with clocking teams and full-chip designers to balance clocks and optimize power delivery.

Skills

Timing analysis

Constraints generation

TFM workflows

TCL scripting

SoC clocking

Power analysis

Digital design

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Job description

Intel Corporation in Santa Clara is seeking a Physical Design Timing Engineer to ensure optimal timing, power efficiency, and performance of SoC designs. You will collaborate with cross-functional teams to develop advanced methodologies and drive timing solutions across chip blocks.

The role requires extensive experience in timing analysis, constraint generation, and clocking flows, with proficiency in TCL scripting, and a strong foundation in digital design and power-performance optimization.