CPU Physical Design Timing Engineer

Qualcomm; Austin (TX); On-site; USD 120,000 - 155,000; Full time

Job summary

Qualcomm seeks a CPU Physical Design Timing Engineer to drive high-performance, low-power CPU implementations for next-generation wireless and mobile SoCs. You will own timing closure for complex CPU blocks, performing constraint development, static timing analysis, ECO implementation, and sign-off across multiple process corners.

Partner closely with RTL, architecture, place-and-route, and PD teams to optimize performance, power, and area.

Qualifications

• Experience driving timing closure for CPU blocks.
• Proficient with constraint development and static timing analysis.
• Experience with ECO implementation and sign-off across process corners.

Responsibilities

• Own timing closure for complex CPU blocks.
• Collaborate with RTL, architecture, and place-and-route teams to optimize timing, power and area.
• Utilize industry EDA tools to resolve timing issues across multiple process corners.

Skills

Timing analysis

Constraint development

Sign-off

Automation

EDA tools

RTL coordination

Place-and-route collaboration

Tools

STA tools

Job description

Qualcomm seeks a CPU Physical Design Timing Engineer to drive high-performance, low-power CPU implementations for next-generation wireless and mobile SoCs. You will own timing closure for complex CPU blocks, performing constraint development, static timing analysis, ECO implementation, and sign-off across multiple process corners. Partner closely with RTL, architecture, place-and-route, and PD teams to optimize performance, power, and area. Use industry EDA tools and advanced nodes to solve challenging timing issues. Contribute to methodology improvements, automation, and best practices in a fast-paced, collaborative engineering culture.