CPU Physical Design Engineer — High-Performance Silicon

Google Inc.; Mountain View, Austin (CA, TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring a Share CPU Physical Design Engineer in Mountain View, CA or Austin, TX. Be part of a team that pushes boundaries, developing custom silicon solutions that power Google's products.

You'll work with RTL, Architecture, and DFT teams to meet timing and power goals, with in-person interviews and a strong emphasis on hardware design at advanced nodes. Individual pay is determined by skills, experience, and education; U.S.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Mentoring juniors

Problem solving

Team collaboration

Communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

Synthesis

Place and Route (PnR)

Static Timing Analysis (STA)

Physical verification

Power checks

Tcl/Python scripting

Job description

Google is hiring a Share CPU Physical Design Engineer in Mountain View, CA or Austin, TX. Be part of a team that pushes boundaries, developing custom silicon solutions that power Google's products.

You'll work with RTL, Architecture, and DFT teams to meet timing and power goals, with in-person interviews and a strong emphasis on hardware design at advanced nodes. Individual pay is determined by skills, experience, and education; U.S.