CPU Physical Design Engineer

Google; United States; On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target 15%

Equity

Benefits

Job summary

Google is seeking a CPU Physical Design Engineer to help deliver custom silicon powering its consumer products. You will drive block-level design from synthesis through PnR and signoff, shaping timing, power, and area for high-performance CPU/SoC blocks.

You will work with RTL, Architecture, and DFT teams, mentoring juniors and contributing to process improvements in advanced nodes. In-person interviews are common as part of the process.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital physical design

Synthesis

Place and Route (PnR)

Timing closure

Education

Bachelor's degree

Master's degree

PhD

Tools

Synthesis tools

Place and Route tools

STA tools

Job description

CPU Physical Design Engineer

Google

Austin, TX, USA; Mountain View, CA, USA.

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Static Timing Analysis (STA), physical verification, or electrical checks using industry-standard tools.
• Experience working on high-performance CPU, GPU, or SoC block-level designs in advanced process nodes (e.g., 5nm or below).
• Proficiency in scripting with Tcl or Python for workflow automation and QoR analysis.
• Understanding of power grid design, EMIR constraints, and low-power implementation techniques.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

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See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.