High-Performance CPU Physical Design Engineer

Google; United States; On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target 15%

Equity

Benefits

Job summary

Google is seeking a CPU Physical Design Engineer to help deliver custom silicon powering its consumer products. You will drive block-level design from synthesis through PnR and signoff, shaping timing, power, and area for high-performance CPU/SoC blocks.

You will work with RTL, Architecture, and DFT teams, mentoring juniors and contributing to process improvements in advanced nodes. In-person interviews are common as part of the process.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital physical design

Synthesis

Place and Route (PnR)

Timing closure

Education

Bachelor's degree

Master's degree

PhD

Tools

Synthesis tools

Place and Route tools

STA tools

Job description

Google is seeking a CPU Physical Design Engineer to help deliver custom silicon powering its consumer products. You will drive block-level design from synthesis through PnR and signoff, shaping timing, power, and area for high-performance CPU/SoC blocks.

You will work with RTL, Architecture, and DFT teams, mentoring juniors and contributing to process improvements in advanced nodes. In-person interviews are common as part of the process.