CPU Physical Design Engineer

Socket.dev; Austin (TX); On-site; USD 138,000 - 197,000; Full time

Job summary

Socket.dev in Austin, Texas is seeking a senior hardware design engineer to execute block-level physical design from synthesis through Place-and-Route and signoff. You will collaborate with RTL, architecture, and DFT teams to meet tight timing, power, and area goals while delivering scalable, high-performance silicon.

Applicants should have 4+ years in digital physical design, strong scripting in Python or Tcl, and hands-on experience with STA and PnR tools.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and signoff tools.

Responsibilities

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.

Skills

Digital PnR & timing

Low-power design experience

Design convergence with industry tools

Education

Bachelor's degree in EE/CE/CS or related

Master's degree or PhD in EE/CE/CS

Tools

STA tooling

Physical verification tools

Python/Tcl scripting

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with digital physical design implementation, including synthesis, Place and Route (PnR), and timing closure.
• Experience in high-performance, low-power physical design implementation or design convergence with industry standard synthesis, PnR and singoff tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Static Timing Analysis (STA), physical verification, or electrical checks using industry-standard tools.
• Experience working on high-performance CPU, GPU, or SoC block-level designs in advanced process nodes (e.g., 5nm or below).
• Proficiency in scripting with Tcl or Python for workflow automation and QoR analysis.
• Understanding of power grid design, EMIR constraints, and low-power implementation techniques.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities:

• Execute block-level physical design implementation from synthesis, Place and Route and design convergence via signoff checks.
• Analyze and resolve timing, congestion, and power issues to achieve optimal Power, Performance, and Area.
• Collaborate with cross-functional teams including RTL, Architecture, and DFT to align design constraints.
• Perform signoff activities, including Static Timing Analysis, physical verification, and power checks.